Datasheet > AD9510BCPZ-REEL7

AD9510BCPZ-REEL7

更新时间： 2024-02-18 02:17:42

品牌	Logo	应用领域
亚德诺 - ADI		时钟
页数	文件大小	规格书
60页	589K
描述
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

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AD9510BCPZ-REEL7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC64,.35SQ,20	针数：	64
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.34
系列：	9510	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-XQCC-N64	JESD-609代码：	e3
长度：	9 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	3	功能数量：	1
反相输出次数：		端子数量：	64
实输出次数：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC64,.35SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	3.3 V
Prop。Delay @ Nom-Sup：	0.695 ns	传播延迟（tpd）：	1.76 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	1.43 ns
座面最大高度：	1 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	BICMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	9 mm
最小 fmax：	1200 MHz

AD9510BCPZ-REEL7 数据手册

1.2 GHz Clock Distribution IC, PLL Core,

Dividers, Delay Adjust, Eight Outputs

AD9510

FEATURES

FUNCTIONAL BLOCK DIAGRAM

VS GND

RSET

CPRSET VCP

Low phase noise phase-locked loop core

Reference input frequencies to 250 MHz

Programmable dual-modulus prescaler

Programmable charge pump (CP) current

Separate CP supply (VCP_S) extends tuning range

Two 1.6 GHz, differential clock inputs

8 programmable dividers, 1 to 32, all integers

Phase select for output-to-output coarse delay adjust

4 independent 1.2 GHz LVPECL outputs

Additive output jitter 225 fs rms

PLL

REF

DISTRIBUTION

REF

AD9510

REFIN

R DIVIDER

N DIVIDER

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

REFINB

SYNCB,

RESETB

PDB

FUNCTION

PLL

SETTINGS

STATUS

CLK1

CLK2

CLK2B

CLK1B

PROGRAMMABLE

DIVIDERS AND

PHASE ADJUST

LVPECL

OUT0

/1, /2, /3... /31, /32

OUT0B

4 independent 800 MHz/250 MHz LVDS/CMOS clock outputs

Additive output jitter 275 fs rms

Fine delay adjust on 2 LVDS/CMOS outputs

Serial control port

OUT1

OUT1B

LVPECL

OUT2

OUT2B

SCLK

SDIO

SDO

CSB

LVPECL

Space-saving 64-lead LFCSP

SERIAL

CONTROL

PORT

OUT3

OUT3B

LVDS/CMOS

OUT4

APPLICATIONS

OUT4B

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

OUT5

OUT5B

OUT6

OUT6B

Broadband infrastructure

OUT7

OUT7B

Figure 1.

Each output has a programmable divider that may be bypassed

or set to divide by any integer up to 32. The phase of one clock

output relative to another clock output may be varied by means

of a divider phase select function that serves as a coarse timing

adjustment. Two of the LVDS/CMOS outputs feature

programmable delay elements with full-scale ranges up to 10 ns

of delay. This fine tuning delay block has 5-bit resolution, giving

32 possible delays from which to choose for each full-scale

setting.

GENERAL DESCRIPTION

The AD9510 provides a multi-output clock distribution

function along with an on-chip PLL core. The design emphasizes

low jitter and phase noise to maximize data converter

performance. Other applications with demanding phase noise

and jitter requirements also benefit from this part.

The PLL section consists of a programmable reference divider

(R); a low noise phase frequency detector (PFD); a precision

charge pump (CP); and a programmable feedback divider (N).

By connecting an external VCXO or VCO to the CLK2/CLK2B

pins, frequencies up to 1.6 GHz may be synchronized to the

input reference.

The AD9510 is ideally suited for data converter clocking

applications where maximum converter performance is

achieved by encode signals with subpicosecond jitter.

The AD9510 is available in a 64-lead LFCSP and can be

operated from a single 3.3 V supply. An external VCO, which

requires an extended voltage range, can be accommodated

by connecting the charge pump supply (VCP) to 5.5 V. The

temperature range is −40°C to +85°C.

There are eight independent clock outputs. Four outputs are

LVPECL (1.2 GHz), and four are selectable as either LVDS

(800 MHz) or CMOS (250 MHz) levels.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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