14-Bit, 80 MSPS/105 MSPS/125 MSPS,
1.8 V Analog-to-Digital Converter
AD9246
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AVDD
DRVDD
1.8 V analog supply operation
1.8 V to 3.3 V output supply
AD9246
SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input
SFDR = 85 dBc to 70 MHz input
Low power: 395 mW @ 125 MSPS
Differential input with 650 MHz bandwidth
On-chip voltage reference and sample-and-hold amplifier
DNL = 0.4 LSB
VIN+
VIN–
8-STAGE
MDAC1
A/D
3
SHA
1 1/2-BIT PIPELINE
4
8
A/D
REFT
REFB
CORRECTION LOGIC
OR
15
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary, Gray code, or twos complement data format
Clock duty cycle stabilizer
OUTPUT BUFFERS
DCO
D13 (MSB)
D0 (LSB)
VREF
Data output clock
Serial port control
Built-in selectable digital test pattern generation
Programmable clock and data alignment
SENSE
SCLK/DFS
SDIO/DCS
CSB
CLOCK
0.5V
MODE
SELECT
DUTY CYCLE
STABILIZER
REF
SELECT
AGND
CLK+ CLK–
PDWN DRGND
APPLICATIONS
Ultrasound equipment
Figure 1.
IF sampling in communications receivers
IS-95, CDMA-One, IMT-2000
Battery-powered instruments
Hand-held scopemeters
The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic.
Low cost digital oscilloscopes
GENERAL DESCRIPTION
The AD9246 is available in a 48-lead LFCSP_VQ and is specified
over the industrial temperature range (−40°C to +85°C).
The AD9246 is a monolithic, single 1.8 V supply, 14-bit, 80 MSPS/
105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring
a high performance sample-and-hold amplifier (SHA) and on-chip
voltage reference. The product uses a multistage differential
pipeline architecture with output error correction logic to
provide 14-bit accuracy at 125 MSPS data rates and guarantees
no missing codes over the full operating temperature range.
PRODUCT HIGHLIGHTS
1. The AD9246 operates from a single 1.8 V power supply
and features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets, including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9246 is suitable for applications in communications,
imaging, and medical ultrasound.
2. The patented SHA input maintains excellent performance
for input frequencies up to 225 MHz.
3. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
4. A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or Gray coding), enabling the
clock DCS, power-down, and voltage reference mode.
A differential clock input controls all internal conversion cycles.
A duty cycle stabilizer (DCS) compensates for wide variations in
the clock duty cycle while maintaining excellent overall ADC
performance.
5. The AD9246 is pin-compatible with the AD9233, allowing
a simple migration from 12 bits to 14 bits.
Rev. A
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