12-Bit, 20 MSPS/40 MSPS/65 MSPS
Dual A/D Converter
AD9238
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Integrated dual 12-bit ADC
AVDD AGND
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70 dB (to Nyquist, AD9238-65)
SFDR = 80.5 dBc (to Nyquist, AD9238-65)
Low power: 300 mW/channel at 65 MSPS
Differential input with 500 MHz, 3 dB bandwidth
Exceptional crosstalk immunity > 85 dB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
OTR_A
VIN+_A
VIN–_A
12
12
D11_A TO D0_A
OEB_A
SHA
ADC
OUTPUT
MUX/
BUFFERS
REFT_A
REFB_A
VREF
MUX_SELECT
CLK_A
CLOCK
DUTY CYCLE
STABILIZER
CLK_B
DCS
SENSE
AGND
SHARED_REF
PWDN_A
PWDN_B
DFS
0.5V
Output datamux option
MODE
CONTROL
REFT_B
REFB_B
VIN+_B
VIN–_B
APPLICATIONS
Ultrasound equipment
Direct conversion or IF sampling receivers
WB-CDMA, CDMA2000, WiMAX
Battery-powered instruments
Hand-held scopemeters
OTR_B
12
12
OUTPUT
MUX/
BUFFERS
SHA
ADC
D11_B TO D0_B
OEB_B
AD9238
DRVDD
DRGND
Low cost, digital oscilloscopes
Figure 1.
GENERAL DESCRIPTION
Fabricated on an advanced CMOS process, the AD9238 is
available in a Pb-free, space saving, 64-lead LQFP or LFCSP and
is specified over the industrial temperature range (−40°C to
+85°C).
The AD9238 is a dual, 3 V, 12-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter (ADC). It features dual high
performance sample-and-hold amplifiers (SHAs) and an
integrated voltage reference. The AD9238 uses a multistage
differential pipelined architecture with output error correction
logic to provide 12-bit accuracy and to guarantee no missing
codes over the full operating temperature range at up to
65 MSPS data rates. The wide bandwidth, differential SHA
allows for a variety of user-selectable input ranges and offsets,
including single-ended applications. It is suitable for various
applications, including multiplexed systems that switch full-
scale voltage levels in successive channels and for sampling
inputs at frequencies well beyond the Nyquist rate.
PRODUCT HIGHLIGHTS
1. Pin-compatible with the AD9248, 14-bit 20MSPS/
40 MSPS/65 MSPS ADC.
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS
allow flexibility between power, cost, and performance to suit
an application.
3. Low power consumption:
•
•
•
AD9238-65: 65 MSPS = 600 mW
AD9238-40: 40 MSPS = 330 mW
AD9238-20: 20 MSPS = 180 mW
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available and can
compensate for wide variations in the clock duty cycle, allowing
the converter to maintain excellent performance. The digital
output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to
determine low or high overflow.
4. Typical channel isolation of 85 dB @ fIN = 10 MHz.
5. The clock duty cycle stabilizer (AD9238-20/AD9238-40/
AD9238-65) maintains performance over a wide range of
clock duty cycles.
6. Multiplexed data output option enables single-port operation
from either Data Port A or Data Port B.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
©2005 Analog Devices, Inc. All rights reserved.
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