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AD8382

更新时间： 2024-02-25 00:27:28
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 868K
描述
High Performance 12-Bit, 6-Channel Output, Decimating LCD DecDriver

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AD8382 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：QFN
包装说明：7 X 7 MM, MO-220-VKKD-2, LFCSP-48针数：48
Reach Compliance Code：unknown风险等级：5.77
数据输入模式：PARALLEL接口集成电路类型：LIQUID CRYSTAL DISPLAY DRIVER
JESD-30 代码：S-PQCC-N48JESD-609代码：e0
长度：7 mm湿度敏感等级：NOT SPECIFIED
复用显示功能：NO功能数量：1
区段数：6端子数量：48
最高工作温度：85 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：COMMERCIAL
座面最大高度：1 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
电源电压1-最大：18 V电源电压1-分钟：9 V
电源电压1-Nom：15.5 V表面贴装：YES
温度等级：OTHER端子面层：TIN LEAD
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmBase Number Matches：1

AD8382 数据手册

 浏览型号AD8382的Datasheet PDF文件第4页浏览型号AD8382的Datasheet PDF文件第5页浏览型号AD8382的Datasheet PDF文件第6页浏览型号AD8382的Datasheet PDF文件第8页浏览型号AD8382的Datasheet PDF文件第9页浏览型号AD8382的Datasheet PDF文件第10页 
AD8382  
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS  
DB0  
DB1  
DB2  
DB3  
DB4  
DB5  
DB6  
DB7  
DB8  
1
2
3
4
5
6
7
8
9
36 VID0  
35 AVCC0,1  
34 VID1  
33 AGND1,2  
32 VID2  
31 AVCC2,3  
30 VID3  
PIN 1  
INDICATOR  
AD8382  
TOP VIEW  
(Not to Scale)  
29 AGND3,4  
28 VID4  
DB9 10  
DB10 11  
DB11 12  
27 AVCC4,5  
26 VID5  
25 AGND5  
NC = NO CONNECT  
Figure 6. 48-Lead LFCSP, 7 mm × 7 mm Package  
Table 4. Pin Function Descriptions  
Mnemonic  
DB(0:11)  
CLK  
Function  
Data Input  
Clock  
Description  
12-Bit Data Input. MSB = DB(11).  
Clock Input.  
STSQ  
Start Sequence  
A new data loading sequence begins on the rising edge of CLK when this input was HIGH on  
the preceding rising edge of CLK and the E/O input is held HIGH. A new data loading sequence  
begins on the falling edge of CLK when this input was HIGH on the preceding falling edge of  
CLK and the E/O input is held LOW.  
R/L  
Right/Left Select  
Even/Odd Select  
A new data loading sequence begins on the left, with Channel 0, when this input is LOW, and  
on the right, with Channel 5, when this input is HIGH.  
E/O  
The active CLK edge is the rising edge when this input is held HIGH and the falling edge when  
this input is held LOW. Data is loaded sequentially on the rising edges of CLK when this input is  
HIGH and on the falling edges when this input is LOW.  
XFR  
Data Transfer  
Data is transferred to the outputs on the immediately following falling edge of CLK when this  
input is HIGH on the rising edge of CLK.  
VID0–VID5  
V1,V2  
Analog Outputs  
These pins are directly connected to the analog inputs of the LCD panel.  
Reference Voltages  
The voltages applied between these pins and AGND set the reference levels of the analog  
outputs.  
VREFHI,  
VREFLO  
Full-Scale References  
Invert  
The voltage applied between these pins sets the full-scale output voltage.  
INV  
When this pin is HIGH, the analog output voltages are at or above V2. When this pin is LOW,  
the analog output voltages are at or below V1.  
DVCC  
DGND  
AVCCx  
AGNDx  
BYP  
Digital Power Supply  
Digital Supply Return  
Analog Power Supplies  
Analog Supply Returns  
Bypass  
Digital Power Supply.  
This pin is normally connected to the analog ground plane.  
Analog Power Supplies.  
Analog Supply Returns.  
A 0.1 µF capacitor connected between this pin and AGND ensures optimum settling time.  
When HIGH, the internal circuits are debiased and the power dissipation drops to a minimum.  
STBY  
Standby  
Rev. 0 | Page 7 of 24  
 
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