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AD8320ARPZ PDF预览

AD8320ARPZ

更新时间: 2024-02-02 06:53:17
品牌 Logo 应用领域
亚德诺 - ADI 驱动器
页数 文件大小 规格书
20页 584K
描述
IC SPECIALTY TELECOM CIRCUIT, PDSO20, SOIC-20, Telecom IC:Other

AD8320ARPZ 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.33.00.01风险等级:5.67
Is Samacsys:NJESD-30 代码:R-PDSO-G20
JESD-609代码:e3湿度敏感等级:5
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
最大压摆率:105 mA标称供电电压:12 V
表面贴装:YES技术:BIPOLAR
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子位置:DUAL处于峰值回流温度下的最长时间:40
Base Number Matches:1

AD8320ARPZ 数据手册

 浏览型号AD8320ARPZ的Datasheet PDF文件第11页浏览型号AD8320ARPZ的Datasheet PDF文件第12页浏览型号AD8320ARPZ的Datasheet PDF文件第13页浏览型号AD8320ARPZ的Datasheet PDF文件第15页浏览型号AD8320ARPZ的Datasheet PDF文件第16页浏览型号AD8320ARPZ的Datasheet PDF文件第17页 
AD8320  
Var ying Gain by Var ying Load Im pedance  
and tested to demonstrate the specified high speed performance  
of the device. Figure 51 shows the schematic of the evaluation  
board. T he silkscreen for the component side layer is shown in  
Figure 52. T he layout of the board is shown in Figure 53 and  
Figure 54.  
As already mentioned, the AD8320 has a dynamic output im-  
pedance of 75 . T he specified gain range assumes that the  
output is terminated with a 75 load impedance. Varying the  
load impedance allows the gain to be varied, up to a maximum  
of twice the specified gain (for RL  
= ϱ). T he variation in gain  
T he evaluation board package includes a fully populated board  
with BNC-type connectors along with Windows®-based soft-  
ware for controlling the board from a PC’s printer port via a  
standard printer cable.  
with load resistance is shown in Figure 50 for the case of a gain  
control word of 255Dec (i.e., max gain).  
32  
30  
28  
26  
24  
22  
20  
A prototyping area is provided to allow for additional circuitry  
on the board. The single supply and ground to the board are  
brought over to this area and are available on two strips. T here  
are also two extra strips available on the prototyping area which  
can be used for additional power supplies.  
T he board should be powered with a good quality (i.e., low  
noise) single supply of between +5 V and +12 V. Extensive  
decoupling is provided on the board. A 10 µF capacitor, located  
fairly close to the device, provides good decoupling for lower  
frequency signals. In addition, and more importantly, five  
0.1 µF decoupling capacitors are located close to each of the  
five power supply pins (7, 8, 9, 17 and 20).  
0
100  
1000  
10000  
Contr olling the Evaluation Boar d fr om a P C  
R
⍀  
LOAD  
T he evaluation board ships with Windows-based control soft-  
ware. A standard printer cable can be used to connect the  
evaluation board to a PC’s printer port (also called parallel  
port). T he cable length should be kept to less than about 5 feet.  
T he wiring of a standard printer cable, with respect to the sig-  
nal lines that are used in this application, is shown in Figure 55.  
Although the software controls the evaluation board via the  
PCs parallel port, the AD8320 digital interface is serial. T hree  
of the parallel port’s eight bits (and one digital ground line) are  
used to implement this serial interface. A fourth bit is used to  
control the PD pin.  
Figure 50. Gain vs. RLOAD (Gain Control Word = 255Dec)  
T he gain can be described by the following equation:  
2 RLOAD  
AV = 20 log10  
0.316 +0.077 × Code  
(
)
RLOAD +75  
where Code is the decimal equivalent of the 8-bit word.  
Evaluation Boar d  
A two layer evaluation board for the AD8320 is available (part  
number AD8320-EB). T his board has been carefully laid out  
VCC  
C7  
C3  
0.1F  
C6  
0.1F  
C5  
0.1F  
C4  
0.1F  
C2  
0.1F  
C11  
0.1F  
10F  
TP2  
TP4  
VCC  
VCC  
VCC  
VCC  
GND  
BYP  
VCC  
VREF  
C10  
0.1F  
OUTPUT  
VOCM  
VOUT  
AD8320  
C12  
0.1F  
REFERENCE  
TP3  
TP1  
C1  
0.1F  
VREF  
VIN  
ATTENUATOR CORE  
DATA LATCH  
C8  
0.1F  
VOCM  
R1  
115⍀  
INPUT  
POWER-  
DOWN  
/
PD  
SWITCH  
INTER  
DATA SHIFT REGISTER  
SDATA  
GND GNDGND GNDGND  
CLK  
DATEN  
R4  
0
C9  
OPTIONAL  
3
5
2
16, 19-30, 33  
6
36-PIN CENTRONICS CONNECTOR  
Figure 51. Evaluation Board Schem atic  
All trademarks are the property of their respective holders.  
–14–  
REV. 0  

AD8320ARPZ 替代型号

型号 品牌 替代类型 描述 数据表
AD8320ARP-REEL ADI

完全替代

IC SPECIALTY TELECOM CIRCUIT, PDSO20, SOIC-20, Telecom IC:Other
AD8320ARPZ-REEL ADI

类似代替

IC SPECIALTY TELECOM CIRCUIT, PDSO20, SOIC-20, Telecom IC:Other

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