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AD8029AKS-REEL PDF预览

AD8029AKS-REEL

更新时间: 2024-01-14 22:46:08
品牌 Logo 应用领域
亚德诺 - ADI 放大器
页数 文件大小 规格书
20页 883K
描述
Low Power, High Speed Rail-to-Rail Input/Output Amplifier

AD8029AKS-REEL 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.08
放大器类型:OPERATIONAL AMPLIFIER架构:VOLTAGE-FEEDBACK
25C 时的最大偏置电流 (IIB):2.8 µA标称共模抑制比:90 dB
频率补偿:YES最大输入失调电压:6000 µV
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm低-偏置:NO
低-失调:NO微功率:NO
湿度敏感等级:1负供电电压上限:-6.3 V
标称负供电电压 (Vsup):-5 V功能数量:1
端子数量:8最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
功率:NO电源:+-1.35/+-6/2.7/12 V
可编程功率:NO认证状态:Not Qualified
座面最大高度:1.75 mm标称压摆率:63 V/us
子类别:Operational Amplifier最大压摆率:1.5 mA
供电电压上限:6.3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BIPOLAR
温度等级:AUTOMOTIVE端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
最小电压增益:1580宽带:YES
宽度:3.9 mmBase Number Matches:1

AD8029AKS-REEL 数据手册

 浏览型号AD8029AKS-REEL的Datasheet PDF文件第3页浏览型号AD8029AKS-REEL的Datasheet PDF文件第4页浏览型号AD8029AKS-REEL的Datasheet PDF文件第5页浏览型号AD8029AKS-REEL的Datasheet PDF文件第7页浏览型号AD8029AKS-REEL的Datasheet PDF文件第8页浏览型号AD8029AKS-REEL的Datasheet PDF文件第9页 
AD8029/AD8030/AD8040  
ABSOLUTE MAXIMUM RATINGS  
Table 4. AD8029/AD8030/AD8040 Stress Ratings  
PD = Quiescent Power + (Total Drive Power Load Power)  
Parameter  
Rating  
Supply Voltage  
Power Dissipation  
12.6 V  
2
VS VOUT  
VOUT  
RL  
See Figure 6  
VS 0.5 V  
1.8 V  
–65°C to +125°C  
–40°C to +125°C  
300°C  
PD  
=
(
VS × IS  
)
+
×
2
RL  
Common-Mode Input Voltage  
Differential Input Voltage  
Storage Temperature  
Operating Temperature Range  
Lead Temperature Range  
(Soldering 10 sec)  
RMS output voltages should be considered. If RL is referenced to  
VS–, as in single-supply operation, then the total drive power is  
VS × IOUT  
.
If the rms signal levels are indeterminate, consider the worst  
Junction Temperature  
150°C  
case, when VOUT = VS/4 for RL to midsupply:  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
2
(
VS/4  
RL  
)
PD  
=
(
VS × IS +  
)
In single-supply operation with RL referenced to VS–, worst case  
is VOUT = VS/2.  
Airflow will increase heat dissipation, effectively reducing θJA.  
Also, more metal directly in contact with the package leads  
from metal traces, through holes, ground, and power planes will  
reduce the θJA. Care must be taken to minimize parasitic capaci-  
tances at the input leads of high speed op amps, as discussed in  
the PCB Layout section.  
MAXIMUM POWER DISSIPATION  
The maximum safe power dissipation in the AD8029/AD8030/  
AD8040 package is limited by the associated rise in junction  
temperature (TJ) on the die. The plastic encapsulating the die  
locally reaches the junction temperature. At approximately  
150°C, which is the glass transition temperature, the plastic  
changes its properties. Even temporarily exceeding this  
temperature limit may change the stresses that the package  
exerts on the die, permanently shifting the parametric  
performance of the AD8029/AD8030/AD8040. Exceeding a  
junction temperature of 175°C for an extended period can  
result in changes in silicon devices, potentially causing failure.  
Figure 6 shows the maximum safe power dissipation in the  
package versus the ambient temperature for the SOIC-8  
(125°C/W), SOT23-8 (160°C/W), SOIC-14 (90°C/W),  
TSSOP-14 (120°C/W), and SC70-6 (208°C/W) packages on a  
JEDEC standard 4-layer board. θJA values are approximations.  
2.5  
The still-air thermal properties of the package and PCB (θJA),  
ambient temperature (TA), and the total power dissipated in the  
package (PD) determine the junction temperature of the die. The  
junction temperature can be calculated as  
2.0  
SOIC-14  
1.5  
TSSOP-14  
TJ = TA + (PD × θJA)  
SOIC-8  
1.0  
SOT-23-8  
The power dissipated in the package (PD) is the sum of the  
quiescent power dissipation and the power dissipated in the  
package due to the load drive for all outputs. The quiescent  
power is the voltage between the supply pins (VS) times the  
quiescent current (IS). Assuming the load (RL) is referenced to  
midsupply, the total drive power is VS/2 × IOUT, some of which is  
dissipated in the package and some in the load (VOUT × IOUT).  
The difference between the total drive power and the load  
power is the drive power dissipated in the package.  
SC70-6  
0.5  
0
–40302010  
0
10 20 30 40 50 60 70 80 90 100 110120  
AMBIENT TEMPERATURE (°C)  
Figure 6. Maximum Power Dissipation  
Output Short Circuit  
Shorting the output to ground or drawing excessive current  
from the AD8029/AD8030/AD8040 could cause catastrophic  
failure.  
Rev. A | Page 6 of 20  
 
 

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