3 V to 5 V Single Supply, 200 kSPS
12-Bit Sampling ADC
a
AD7854/AD7854L*
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Specified for VDD of 3 V to 5.5 V
Read-Only Operation
AV
AGND
DD
AD7854–200 kSPS; AD7854L–100 kSPS
System and Self-Calibration with Autocalibration on
Power-Up
AIN(+)
AIN(–)
AD7854/AD7854L
T/H
2.5V
REFERENCE
Low Power
DV
DD
AD7854: 15 mW (VDD = 3 V)
AD7854L: 5.5 mW (VDD = 3 V)
Automatic Power-Down After Conversion (25 W)
Flexible Parallel interface
12-Bit Parallel / 8-Bit Parallel (AD7854)
28-Pin DIP, SOIC and SSOP Packages (AD7854)
COMP
BUF
REF
/
IN
REF
OUT
C
REF1
DGND
CHARGE
REDISTRIBUTION
DAC
APPLICATIONS
C
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems
REF2
CLKIN
CONVST
BUSY
SAR + ADC
CONTROL
CALIBRATION
MEMORY
AND CONTROLLER
PARALLEL INTERFACE/CONTROL REGISTER
GENERAL DESCRIPTION
DB11–DB0
HBEN
CS
RD
WR
The AD7854/AD7854L is a high speed, low-power, 12-bit
ADC which operates from a single 3 V or 5 V power supply, the
AD7854 being optimized for speed and the AD7854L for low
power. The ADC powers up with a set of default conditions at
which time it can be operated as a read-only ADC. The ADC
contains self-calibration and system calibration options to en-
sure accurate operation over time and temperature and has a
number of power-down options for low power applications.
PRODUCT HIGHLIGHTS
1. Operation with either 3 V or 5 V power supplies.
2. Automatic calibration on power-up.
3. Flexible power management options including automatic
power-down after conversion.
The AD7854 is capable of 200 kHz throughput rate while the
AD7854L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo-
differential sampling scheme. The AD7854 and AD7854L input
voltage range is 0 to VREF (unipolar) and –VREF/2 to +VREF/2,
centered at VREF/2 (bipolar). The coding is straight binary in
unipolar mode and twos complement in bipolar mode. Input
signal range is to the supply and the part is capable of convert-
ing full-power signals to 100 kHz.
4. Operates with reference voltages from 1.2 V to AVDD
.
5. Analog input ranges from 0 V to AVDD
6. Self- and system-calibration.
7. Versatile parallel I/0 port.
.
8. Lower power version AD7854L.
CMOS construction ensures low power dissipation of typically
5.4 mW for normal operation and 3.6 µW in power-down mode.
The part is available in 28-pin, 0.3 inch wide dual-in-line pack-
age (DIP), 28-lead small outline (SOIC) and 28-lead small
shrink outline (SSOP) packages.
*Patent pending.
See Page 35 for data sheet index.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
PRELIMINARY TECHNICAL DATA
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