LC2MOS
Quad 14-Bit DACs
AD7834/AD7835
FSYNC
into one via DIN, SCLK, and
. The AD7834 has five
FEATURES
dedicated package address pins, PA0 to PA4, that can be ꢂired
to AGND or ꢁCC to permit up to 39 AD7834s to be individually
addressed in a multipackage application.
Four 14-bit DACs in one package
AD7834—serial loading
AD7835—parallel 8-bit/14-bit loading
Voltage outputs
The AD7835 can accept either 14-bit parallel loading or double-
byte loading, ꢂhere right-justified data is loaded in one 8-bit
byte and one 6-bit byte. Data is loaded from the external bus
Power-on reset function
Maximum/minimum output voltage range of 8.192 V
Maximum output voltage span of 14 V
Common voltage reference inputs
User-assigned device addressing
Clear function to user-defined voltage
Surface-mount packages
WR CS
into one of the input latches under the control of the
,
,
BYSHF
, and DAC channel address pins, A0 to A9.
LDAC
With each device, the
signal is used to update all four
DAC outputs simultaneously, or individually, on reception of
CLR
neꢂ data. In addition, for each device, the asynchronous
AD7834—28-lead SOIC and PDIP
AD7835—44-lead MQFP and PLCC
input can be used to set all signal outputs, ꢁOUT1 to ꢁOUT4, to
the user-defined voltage level on the device sense ground pin,
DSG. On poꢂer-on, before the poꢂer supplies have stabilized,
internal circuitry holds the DAC output voltage levels to ꢂithin
9 ꢁ of the DSG potential. As the supplies stabilize, the DAC
APPLICATIONS
Process control
Automatic test equipment
General-purpose instrumentation
CLR
output levels move to the exact DSG potential (assuming
exercised).
is
GENERAL DESCRIPTION
The AD7834 is available in a 98-lead 0.3" SOIC package and a
98-lead 0.6" PDIP package, and the AD7835 is available in a
44-lead MQFP package and a 44-lead PLCC package.
The AD7834 and AD7835 contain four 14-bit DACs on one
monolithic chip. The AD7834 and AD7835 have output
voltages in the range 8.1ꢀ9 ꢁ ꢂith a maximum span of 14 ꢁ.
The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after tꢂo leading 0s,
FUNCTIONAL BLOCK DIAGRAMS
V
V
(–)A
V
REF
V
V
(+)A
DSGA
REF
V
V (–)
V
REF
V
V
(+)
REF
CC
DD
SS
CC
DD
SS
AD7835
INPUT
REGISTER
1
INPUT
AD7834
DAC 1
DAC 1
DAC 1
DAC 2
DAC 1
DAC 2
REGISTER
1
LATCH
LATCH
BYSHF
PAEN
×1
×1
V
V
1
2
×1
×1
V
1
2
OUT
OUT
OUT
14
DB13
DB0
INPUT
BUFFER
PA0
PA1
INPUT
REGISTER
2
INPUT
REGISTER
2
DAC 2
LATCH
DAC 2
LATCH
CONTROL
LOGIC
AND
ADDRESS
DECODE
V
WR
CS
OUT
PA2
PA3
PA4
INPUT
REGISTER
3
DAC 3
LATCH
INPUT
REGISTER
3
DAC 3
DAC 4
DAC 3
LATCH
DAC 3
DAC 4
×1
×1
V
V
3
4
OUT
OUT
×1
×1
V
3
4
OUT
A0
A1
A2
FSYNC
INPUT
REGISTER
4
ADDRESS
DECODE
DAC 4
LATCH
INPUT
REGISTER
4
DAC 4
LATCH
SERIAL-TO-
PARALLEL
CONVERTER
DIN
V
OUT
CLR
SCLK
CLR
DSGB
(+)B
AGND
DGND
V
(–)B
V
LDAC
AGND
DGND
LDAC
DSG
REF
REF
Figure 1. AD7834
Figure 2. AD7835
Rev. D
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