LC2MOS
Quad 14-Bit DACs
AD7834/AD7835
The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after two leading
FEATURES
Four 14-bit DACs in one package
AD7834—serial loading
0s, into one via DIN, SCLK, and
.
FSYNC
AD7835—parallel 8-bit/14-bit loading
Voltage outputs
Power-on reset function
Max/Min output voltage range of 8.192 V
Maximum output voltage span of 14 V
Common voltage reference inputs
User-assigned device addressing
Clear function to user-defined voltage
Surface-mount packages
The AD7834 has five dedicated package address pins, PA0 to
PA4, that can be wired to AGND or VCC to permit up to 32
AD7834s to be individually addressed in a multipackage
application.
The AD7835 can accept either 14-bit parallel loading or double-
byte loading, where right-justified data is loaded in one 8-bit
byte and one 6-bit byte. Data is loaded from the external bus
into one of the input latches under the control of the
,
,
WR CS
, and DAC channel address pins, A0 to A2.
BYSHF
AD7834—28-lead SOIC and PDIP
AD7835—44-lead MQFP and PLCC
With each device, the
signal is used to update all four
LDAC
APPLICATIONS
Process control
Automatic test equipment
General purpose instrumentation
DAC outputs simultaneously, or individually, on reception of
new data. In addition, for each device, the asynchronous
CLR
input can be used to set all signal outputs, VOUT1 to VOUT4, to
the user-defined voltage level on the Device Sense Ground pin,
DSG. On power-on, before the power supplies have stabilized,
internal circuitry holds the DAC output voltage levels to within
2 V of the DSG potential. As the supplies stabilize, the DAC
output levels move to the exact DSG potential (assuming
is exercised).
GENERAL DESCRIPTION
The AD7834 and AD7835 parts contain four 14-bit DACs on
one monolithic chip. The AD7834 and AD7835 have out-
put voltages in the range of 8.192 V with a maximum
span of 14 V.
CLR
The AD7834 is available in 28-lead 0.3" SOIC package and
28-lead 0.6" PDIP package, and the AD7835 is available in a
44-lead MQFP package and a 44-lead PLCC package.
AD7834 FUNCTIONAL BLOCK DIAGRAM
AD7835 FUNCTIONAL BLOCK DIAGRAM
V
V
(–)
V
V
(–)A
V
REF
V
V
V
(+)
V
V
(+)A
DSG A
REF
CC
REF
CC
DD
SS
REF
DD
SS
INPUT
AD7835
AD7834
INPUT
DAC 1
DAC 1
DAC 1
DAC 2
REGISTER
1
DAC 1
DAC 2
REGISTER
1
LATCH
LATCH
PAEN
BYSHF
×
×
1
1
×1
×1
V
1
2
V
V
1
2
OUT
OUT
14
DB13
DB0
PA0
PA1
INPUT
BUFFER
INPUT
REGISTER
2
INPUT
REGISTER
2
DAC 2
LATCH
DAC 2
LATCH
CONTROL
LOGIC
AND
ADDRESS
DECODE
V
OUT
PA2
PA3
PA4
OUT
WR
CS
INPUT
REGISTER
3
INPUT
REGISTER
3
DAC 3
LATCH
DAC 3
LATCH
DAC 3
DAC 4
DAC 3
DAC 4
×
×
1
1
V
3
4
×1
×1
V
V
3
4
OUT
OUT
FSYNC
A0
A1
A2
INPUT
REGISTER
4
INPUT
REGISTER
4
ADDRESS
DECODE
DAC 4
LATCH
DAC 4
LATCH
SERIAL-TO-
PARALLEL
CONVERTER
DIN
V
OUT
OUT
CLR
SCLK
CLR
AGND
DGND
LDAC
DSG
DSG B
(+)B
AGND
DGND
V
(–)B
REF
V
LDAC
REF
Figure 1.
Figure 2.
Rev. C
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