Datasheet > AD7761BSTZ-RL7

AD7761BSTZ-RL7

更新时间： 2024-11-24 01:11:03

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
76页	1516K
描述
8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW

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AD7761BSTZ-RL7 数据手册

8-Channel, 16-Bit, Simultaneous Sampling

ADC with Power Scaling, 110.8 kHz BW

AD7761

Data Sheet

Linear phase digital filter

FEATURES

Low latency sinc5 filter

Precision ac and dc performance

8-channel simultaneous sampling

256 kSPS ADC ODR per channel

97.7 dB dynamic range

110.8 kHz input bandwidth (−3 dB BW)

−120 dB THD, typical

Wideband brick wall filter: 0.005 dB ripple to 102.4 kHz

Analog input precharge buffers

Power supply

AVDD1 = 5 V, AVDD2 = 2.25 V to 5.0 V

IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V

64-lead LQFP package, no exposed pad

1 LSB INL, 1 LSB offset error, 5 LSB gain error

Optimized power dissipation vs. noise vs. input bandwidth

Selectable power, speed, and input bandwidth

Fast (highest speed): 110.8 kHz BW, 51.5 mW per channel

Median (half speed): 55.4 kHz BW, 27.5 mW per channel

Low power (lowest power): 13.8 kHz BW, 9.375 mW per

channel

Temperature range: −40°C to +105°C

APPLICATIONS

Data acquisition systems: USB/PXI/Ethernet

Instrumentation and industrial control loops

Audio testing and measurement

Vibration and asset condition monitoring

3-phase power quality analysis

Input BW range: dc to 110.8 kHz

Programmable input bandwidth/sampling rates

CRC error checking on data interface

Sonar

High precision medical electroencephalogram (EEG)/

electromyography (EMG)/electrocardiogram (ECG)

Daisy-chaining

FUNCTIONAL BLOCK DIAGRAM

AVDD1A,

AVDD1B

AVDD2A, REGCAPA,

REFx+ REFx–

AVDD2B REGCAPB DGND

IOVDD

DREGCAP

BUFFERED

VCM

1.8V

LDO

1.8V

LDO

PRECHARGE

REFERENCE

BUFFERS

VCM

×8

VCM

SYNC_IN

SYNC_OUT

START

AIN0+

AIN0–

AIN1+

AIN1–

OFFSET,

Σ-Δ

RESET

DIGITAL

FILTER

ENGINE

CH 0

GAIN PHASE

CORRECTION

ADC

FORMAT1

FORMAT0

OFFSET,

GAIN PHASE

CORRECTION

Σ-Δ

ADC

CH 1

ADC

OUTPUT

DATA

DRDY

SINC5

LOW LATENCY

FILTER

AIN2+

AIN2–

DCLK

SERIAL

OFFSET,

GAIN PHASE

CORRECTION

Σ-Δ

ADC

CH 2

INTERFACE

DOUT0

DOUT1

DOUT2

DOUT3

DOUT4

DOUT5

DOUT6

DOUT7

AIN3+

AIN3–

AIN4+

AIN4–

OFFSET,

GAIN PHASE

CORRECTION

Σ-Δ

ADC

CH 3

CH 4

CH 5

WIDEBAND

LOW RIPPLE

FILTER

OFFSET,

GAIN PHASE

CORRECTION

Σ-Δ

ADC

AIN5+

AIN5–

OFFSET,

GAIN PHASE

CORRECTION

Σ-Δ

ADC

ST0/CS

SPI

ST1/SCLK

DEC0/SDO

DEC1/SDI

CONTROL

INTERFACE

AIN6+

AIN6–

OFFSET,

Σ-Δ

CH 6

CH 7

GAIN PHASE

CORRECTION

ADC

AIN7+

AIN7–

OFFSET,

GAIN PHASE

CORRECTION

Σ-Δ

ADC

PIN/SPI

×16 ANALOG INPUT

PRECHARGE BUFFERS (P)

AD7761

AVSS

XTAL2/MCLK XTAL1

MODE3/GPIO3 FILTER/GPIO4

MODE0/GPIO0

Figure 1.

Rev. A

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

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与AD7761BSTZ-RL7相关器件

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