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AD7762BCP PDF预览

AD7762BCP

更新时间: 2024-01-08 14:00:20
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
28页 458K
描述
IC 1-CH 24-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, QCC48, LFCSP-48, Analog to Digital Converter

AD7762BCP 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:LFCSP-48针数:48
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
最大模拟输入电压:3.25 V最小模拟输入电压:-3.25 V
转换器类型:ADC, DELTA-SIGMAJESD-30 代码:S-XQCC-N48
JESD-609代码:e0长度:7 mm
模拟输入通道数量:1位数:24
功能数量:1端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:BINARY输出格式:PARALLEL, WORD
封装主体材料:UNSPECIFIED封装代码:VQCCN
封装等效代码:LCC48,.27SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, VERY THIN PROFILE峰值回流温度(摄氏度):220
电源:2.5,5 V认证状态:Not Qualified
采样速率:0.625 MHz座面最大高度:0.9 mm
子类别:Analog to Digital Converters标称供电电压:2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
Base Number Matches:1

AD7762BCP 数据手册

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625 kSPS, 24-Bit, 109 dB Σ−Δ ADC  
With On-Chip Buffer  
AD7762  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
V
V
120 dB dynamic range at 78 kHz output data rate  
109 dB dynamic range at 625 kHz output data rate  
112 dB SNR at 78 kHz output data rate  
106 dB SNR at 625 kHz output data rate  
625 kHz maximum fully filtered output word rate  
Programmable over-sampling rate (32× to 256×)  
Fully differential modulator input  
IN– IN+  
MULTIBIT  
AV  
AV  
AV  
AV  
DD1  
DD2  
DD3  
DD4  
DIFF  
Σ-Δ  
MODULATOR  
V
REF+  
RECONSTRUCTION  
BUF  
DECAPA/B  
R
BIAS  
On-chip differential amplifier for signal buffering  
Low-pass finite impulse response (FIR) filter with default or  
user-programmable coefficients  
Overrange alert bit  
Digital offset and gain correction registers  
Filter bypass modes  
PROGRAMMABLE  
DECIMATION  
AD7762  
AGND  
V
DRIVE  
MCLK  
SYNC  
DV  
CONTROL LOGIC  
I/O  
OFFSET AND GAIN  
REGISTERS  
DD  
DGND  
FIR FILTER  
ENGINE  
RESET  
Low power and power-down modes  
Synchronization of multiple devices via SYNC pin  
CS RD/WR DRDY DB0 TO DB15  
Figure 1.  
APPLICATIONS  
Data acquisition systems  
Vibration analysis  
Instrumentation  
GENERAL DESCRIPTION  
The AD7762 is a high performance, 24-bit Σ-Δ analog-to-  
digital converter (ADC). It combines wide input bandwidth  
and high speed with the benefits of Σ-Δ conversion with a  
performance of 106 dB SNR at 625 kSPS, making it ideal for  
high speed data acquisition. Wide dynamic range combined  
with significantly reduced antialiasing requirements simplify  
the design process. An integrated buffer to drive the reference,  
a differential amplifier for signal buffering and level shifting, an  
overrange flag, internal gain and offset registers, and a low-pass  
digital FIR filter make the AD7762 a compact, highly integrated  
data acquisition device requiring minimal peripheral com-  
ponent selection. In addition, the device offers programmable  
decimation rates, and the digital FIR filter can be adjusted if  
the default characteristics are not appropriate to the application.  
The AD7762 is ideal for applications demanding high SNR  
without a complex front end signal processing design.  
coefficients. The sample rate, filter corner frequencies, and output  
word rate are set by a combination of the external clock frequency  
and the configuration registers of the AD7762.  
The reference voltage supplied to the AD7762 determines the  
analog input range. With a 4 V reference, the analog input range  
is ±±.2 V differential biased around a common mode of 2 V.  
This common-mode biasing can be achieved using the on-chip  
differential amplifier, further reducing the external signal  
conditioning requirements.  
The AD7762 is available in an exposed paddle, 64-lead TQFP  
and is specified over the industrial temperature range from  
−40°C to +85°C.  
Table 1. Related Devices  
Part No.  
AD7760  
AD7763  
Description  
24-bit, 2.5 MSPS, 100 dB Σ-Δ, parallel interface  
24-bit, 625 kSPS, 109 dB Σ-Δ, serial interface  
The differential input is sampled at up to 40 MSPS by an analog  
modulator. The modulator output is processed by a series of low-  
pass filters, the final filter having default or user-programmable  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  
 

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