Pseudo Differential Input, 1 MSPS,
10- and 12-Bit ADCs in an 8-Lead SOT-23
AD7441/AD7451
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fast throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power at max throughput rate:
4 mW max at 1 MSPS with VDD = 3 V
9.25 mW max at 1 MSPS with VDD = 5 V
Pseudo differential analog input
Wide input bandwidth:
V
DD
V
V
IN+
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
IN–
V
REF
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
SCLK
SDATA
CS
AD7441/AD7451
CONTROL LOGIC
Power-down mode: 1 µA max
8-lead SOT-23 and MSOP packages
APPLICATIONS
GND
Transducer interface
Figure 1.
Battery-powered systems
Data acquisition systems
Portable instrumentation
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
1. Operation with 2.7 V to 5.25 V power supplies.
The AD7441/AD74511 are, respectively, 10-bit and 12-bit high
speed, low power, successive approximation (SAR) analog-to-
digital converters that feature a pseudo differential analog input.
These parts operate from a single 2.7 V to 5.25 V power supply
and achieve very low power dissipation at high throughput rates
of up to 1 MSPS.
2. High throughput with low power consumption. With a 3 V
supply, the AD7441/AD7451 offer 4 mW maximum power
consumption for a 1 MSPS throughput rate.
3. Pseudo differential analog input.
4. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. These parts also
feature a shutdown mode to maximize power efficiency at
lower throughput rates.
The AD7441/AD7451 contain a low noise, wide bandwidth,
differential track-and-hold (T/H) amplifier that handles input
frequencies up to 3.5 MHz. The reference voltage for these
devices is applied externally to the VREF pin and can range from
100 mV to VDD, depending on the power supply and what suits
the application.
5. Variable voltage reference input.
6. No pipeline delays.
CS
7. Accurate control of the sampling instant via a
once-off conversion control.
input and
The conversion process and data acquisition are controlled
CS
using
with microprocessors or DSPs. The input signals are sampled
CS
and the serial clock, allowing the device to interface
8. ENOB > 10 bits typically with 500 mV reference.
on the falling edge of
when the conversion is initiated.
The SAR architecture of these parts ensures that there are no
pipeline delays.
1 Protected by U.S. Patent Number 6,681,332.
Rev. B
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