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AD7452_17

更新时间: 2024-11-08 01:16:27
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亚德诺 - ADI /
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描述
Differential Input, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23

AD7452_17 数据手册

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Differential Input, 555 kSPS  
12-Bit ADC in an 8-Lead SOT-23  
Data Sheet  
AD7452  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
V
Specified for VDD of 3 V and 5 V  
Low power at max throughput rate  
3.3 mW max at 555 kSPS with 3 V supplies  
7.25 mW max at 555 kSPS with 5 V supplies  
Fully differential analog input  
DD  
V
V
IN+  
12-BIT  
SUCCESSIVE  
APPROXIMATION  
ADC  
T/H  
Wide input bandwidth  
IN–  
70 dB SINAD at 100 kHz input frequency  
Flexible power/serial clock speed management  
No pipeline delays  
V
REF  
High speed serial interface  
SCLK  
SPI/QSPI™/MICROWIRE™/DSP compatible  
Power-down mode: 1 μA max  
8-lead SOT-23 package  
SDATA  
AD7452  
CONTROL LOGIC  
CS  
APPLICATIONS  
Transducer interface  
Battery-powered systems  
Data acquisition systems  
Portable instrumentation  
Motor control  
GND  
Figure 1.  
The SAR architecture of this part ensures that there are no  
pipeline delays.  
GENERAL DESCRIPTION  
The AD7452 uses advanced design techniques to achieve very  
low power dissipation.  
The AD74521 is a 12-bit, high speed, low power, successive  
approximation (SAR) analog-to-digital converter that features a  
fully differential analog input. This part operates from a single  
3 V or 5 V power supply and features throughput rates up to  
555 kSPS.  
PRODUCT HIGHLIGHTS  
1. Operation with Either 3 V or 5 V Power Supplies.  
2. High Throughput with Low Power Consumption. With a  
3 V supply, the AD7452 offers 3.3 mW max power  
consumption for 555 kSPS throughput.  
The part contains a low noise, wide bandwidth, differential  
track-and-hold amplifier (T/H) that can handle input  
frequencies up to 3.5 MHz. The reference voltage is applied  
externally to the VREF pin and can be varied from 100 mV to  
3.5 V depending on the power supply and what suits the  
application. The value of the reference voltage determines the  
common-mode voltage range of the part. With this truly  
differential input structure and variable reference input, the  
user can select a variety of input ranges and bias points.  
3. Fully Differential Analog Input.  
4. Flexible Power/Serial Clock Speed Management. The  
conversion rate is determined by the serial clock, allowing  
the power to be reduced as the conversion time is reduced  
through the serial clock speed increase. This part also  
features a shutdown mode to maximize power efficiency at  
lower throughput rates.  
5. Variable Voltage Reference Input.  
6. No Pipeline Delay.  
The conversion process and data acquisition are controlled  
CS  
7. Accurate Control of the Sampling Instant via a  
and Once-Off Conversion Control.  
Input  
CS  
using  
and the serial clock, allowing the device to interface  
with microprocessors or DSPs. The input signals are sampled  
8. ENOB > 8 Bits Typically with 100 mV Reference.  
CS  
on the falling edge of , and the conversion is also initiated at  
this point.  
1 Protected by U.S. Patent Number 6,681,332.  
Rev. C  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2003–2015 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 
 

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