PRELIMINARY TECHNICAL DATA
AD74122
Programmable MCLK Divider
Low Group Delay
It is possible to bypass much of the digital filtering by enabling
the Low Group Delay function in Control Register C. By re-
ducing the amount of filtering the AD74122 applies to input
and output samples the time delay between the sampling inter-
val and when the sample is available is greatly reduced. This
can be of benefit in applications such as telematics where mini-
mal time delays are important. When the Low Group Delay
function is enabled the sample rate becomes IMCLK/128.
Pre-Scaler 2
Pre-Scaler 3
Pre-Scaler 1
/1
/2
/3
/1
/2
/4
/1
/2
/3
IMCLK
MCLK
Control Reg
Figure <MCLK_Divider>
Reference
The AD74122 features an on-chip reference whose nominal
value is 1.125 V. A 10 nF capacitor applied at the REFCAP pin
is necessary to stabilise the referrence. (See Figure
<REFCAP_Int>)
The divider ratios will allow more convenient sample rate
selection from a common MCLK which may be required in
many voice related applications. Control Register B should be
programmed to achieve the desired divider ratios.
Selecting Sample Rates
The sample rate at which the convertor runs is always 256
times the IMCLK rate. IMCLK is the Internal Master Clock
and is the output from the Master Clock Prescaler. The de-
fault sample rate is 48kHz (based on an external MCLK of
12.288MHz). In this mode the ADC modulator is clocked at
3.072MHz and the DAC modulator is clocked at 6.144MHz..
Sample rates which are lower than 256 X MCLK can be
acheived by using the MCLK prescaler.
REFCAP
+
10µF
0.1µF
Example 1: fSAMP = 48 kHz and 8 kHz required
MCLK = 48*103 * 256 = 12.288 MHz to cater for 48 kHz
fSAMP
Figure <REFCAP_Int.eps>
If it is required an external reference can be used as the refer-
ence source of the ADC and DAC sections. This may be desir-
able in situations where multiple devices are required to use the
same value of reference or because of a better temperature
coefficient specifications. The internal reference can be dis-
abled via Control Register A and the external reference applied
at the REFCAP pin (See Figure <REFCAP_Ext>). External
references should be of a suitable value such that the voltage
swing of the inputs or outputs is not effected by being too close
to the power supply rails.
For fSAMP = 8 kHz, it is necessary to use the /3 setting in Pre-
Scaler 1, the /2 setting in Pre-Scaler 2 and pass through in Pre-
Scaler 3. This results in an IMCLK = 8*103 * 256 = 2.048
MHz (= 12.288 MHz/6).
Example 2: fSAMP = 44.1 kHz and 11.025 kHz required
MCLK = 44.1*103 * 256 = 11.2896 MHz to cater for 44.1
kHz fSAMP
For fSAMP = 11.025 kHz, it is necessary to use the /1 setting in
Pre-Scaler 1 and the /4 setting in Pre-Scaler 2 and pass
through in Pre-Scaler 3. This results in an IMCLK =
11.025*103 * 256 = 2.8224 MHz (= 11.2896 MHz/4).
1.125 V
REFCAP
Reseting the AD74122
The AD74122 can be reset by bringing the RESET pin low.
Following a reset the internal circuitry of the AD74122 en-
sures that the internal registers are reset to their default set-
tings and the on-chip RAM is purged of previous data samples.
The DIN pin is sampled to determine if the AD74122 is re-
quired to operate in Master or Slave mode. The reset process
takes 3072 MCLK periods and the user should not attempt to
program the AD74122 during this time.
EXTERNAL
REFERENCE
Figure <REFCAP_Ext.eps>
Master Clocking Scheme
The update rate of the AD74122’s ADC and DAC channels
require an internal master clock (IMCLK) which is 256 times
that sample update rate (IMCLK = 256 * FS). In order to
provide some flexibility in selecting sample rates, the device has
a series of three master clock pre-scalers which are program-
mable and allow the user to choose a range of convenient
sample rates from a single external master clock. The master
clock signal to the AD74122 is applied at the MCLK pin. The
MCLK signal is passed through a series of three programmable
MCLK pre-scalers (divider) circuits which can be selected to
reduce the resulting Internal MCLK (IMCLK) frequency if
required. The first and second MCLK pre-scalers provides
divider ratios of /1 (pass through), /2, /3 while the third pre-
scaler provides divider ratios of /1 (pass through), /2, /4.
REV. PrG
–9–
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