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AD74122YRU PDF预览

AD74122YRU

更新时间: 2024-01-24 01:28:58
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管商用集成电路
页数 文件大小 规格书
18页 346K
描述
IC SPECIALTY CONSUMER CIRCUIT, PDSO20, TSSOP-20, Consumer IC:Other

AD74122YRU 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-20
针数:20Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.5 mm功能数量:1
端子数量:20最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5,3.3 V
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Other Consumer ICs最大供电电压 (Vsup):2.75 V
最小供电电压 (Vsup):2.375 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

AD74122YRU 数据手册

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PRELIMINARY TECHNICAL DATA  
AD74122  
FUNCTIONAL DESCRIPTION  
master or slave device. The AD74122 can also be set to operate  
with sample rates of 8KHz to 48KHz depending on the values  
of MCLK and the MCLK prescalers. On chip digital filtering  
is provided for the DAC and ADC channels with a low group  
delay option to reduce the delays through the filters when  
operating at lower sample rates. Figure <modulators.eps>  
shows a block diagram of a DAC and ADC channel in the  
AD74122. Figure <filter.eps> shows a block diagram of the  
filter arrangement of the ADC and DAC filters.  
General Description  
The AD74122 is a 2.5V stereo codec. It comprises two ADC  
and two DAC channels with single ended inputs and outputs.  
Signal conditioning and programmable gain stages are also  
provided. Each of these sections are described in further detail  
below. The AD74122 is controlled by means of a flexible serial  
interface port (SPORT) which can be programmed to  
accomodate many industry standard DSPs and  
Microcontrollers. The AD74122 can be set to operate as a  
ADC  
INPUT  
MCLK  
SINC  
FILTER  
(/8)  
ADC  
DATA  
PRESCALERS  
(/1 to /12)  
Σ−∆ ADC  
MODULATOR  
DECIMATOR  
(/8)  
/4  
16/20/24  
BITS  
ADC Modulator  
Clock  
Σ−∆ DAC  
MODULATOR  
DAC  
O/P  
/2  
DAC Modulator  
Clock  
5 BITS  
INTERPOLATOR  
( X 8)  
INTERPOLATOR  
( X 16)  
DAC  
DATA  
16/20/24  
BITS  
Figure <modulators.eps>. ADC and DAC Engine  
REV. PrG  
7–  

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