Datasheet > AD74122YRU

AD74122YRU

更新时间： 2024-02-03 09:58:22

品牌	Logo	应用领域
亚德诺 - ADI		光电二极管商用集成电路
页数	文件大小	规格书
18页	346K
描述
IC SPECIALTY CONSUMER CIRCUIT, PDSO20, TSSOP-20, Consumer IC:Other

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数据手册

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AD74122YRU 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	TSSOP-20
针数：	20	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.92	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	R-PDSO-G20	JESD-609代码：	e0
长度：	6.5 mm	功能数量：	1
端子数量：	20	最高工作温度：	105 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP20,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2.5,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.1 mm
子类别：	Other Consumer ICs	最大供电电压 (Vsup)：	2.75 V
最小供电电压 (Vsup)：	2.375 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm	Base Number Matches：	1

AD74122YRU 数据手册

PRELIMINARY TECHNICAL DATA

AD74122

Comb

Compensation

Filter

ADC

Modulator

8 × f

4 × f

2 × f

Halfband

Filter

5th Order

Comb Filter

Halfband

Filter

ADC

Result

Low Group

Delay Ouput

Figure <ADC Filter.eps>. ADC Filter Section

DAC

Modulator

128

Zero Order Hold

Sinc Compensation

Filter

8 × f

2 × f

4 × f

16 X Zero

Order Hold

Halfband

Filter

Halfband

Filter

DAC

Input

Low Group

Delay Input

Figure <dac filter.eps>. DAC Filter Section

Input Signal swing

ADC Section

There are two ADC channels in the AD74122, configured as a

stereo pair. Each ADC channel can be independently muted

under software control. Each ADC has single input pin with

additional pins for decoupling/filter capacitors. Each ADC

channel has an independent input amplifier gain stage which

can be programmed in steps of +3dB, from 0dB to +12dB. The

input amplifier gain settings are set by programming the appro-

priate bits in Control Register E for the left ADC and Control

employ a multi-bit sigma-delta conversion technique, which

provides a high resolution output with system filtering being

implemented on-chip. Sigma-delta converters employ a tech-

nique known as over-sampling, where the sampling rate is many

times the highest frequency of interest. The oversampling ratio

for the ADC is 64 and a decimation filter is used to reduce the

output to standard sample rates. The maximum sample rate is

48kHz.

Each ADC input has an input range of 0.5 V_RMS/ 1.414 V_P-P

about a bias point equal to V_REFCAP(See Figure <ADC_cct>).

The analog input can also be AC coupled to the AD74122 as

shown which will automatically bias the signal to the V_REFCAP

value internally. This allows signals biased around a voltage

other than V_REFCAPto be connected directly to the AD74122.

AGND

1.414 V

VINx

P-P

51⍀

47µF

10nF

NPO

Figure <ADC_cct.eps>.Input Swing

ADC CAPP and CAPN Pins

The ADC channel requires two external capacitors to act as

charge resevoirs for the switched capacitor inputs of the sigma-

delta modulator. These capacitors isolate the outputs of the

PGA stage from glitches generated by the sigma-delta modula-

tor. The capacitor also forms a low pass filter with the output

impedance of the PGA (approximately 124Ω) which helps to

isolate noise from the modulator engine. The capacitors should

be of good quality such as NPO or polyproplene film and values

from 100pF to 1nF are suitable.

DAC Section

The AD74122 has two DAC channels arranged as a stereo pair,

with two, single-ended, analog outputs. Each channel has it’s

own independently programmable attenuator. Control Register

G controls the attenuation factor for the left DAC while Con-

trol Register J controls the attenuation factor for the right

DAC. Each of these registers is 10 bits wide giving 1024 steps

of attenuation. AD74122 output channels employ a multi-bit

sigma-delta conversion technique, which provides a high qual-

ity output with system filtering being implemented on-chip.

Peak Readback

The AD74122 can store the highest ADC value from each

channel in order to facilatate level adjustment of the input

signal. Programming the Peak Enable bit in Control Register H

with a 1 will enable ADC Peak Level Reading. The Peak values

are stored as a 6 bit number from 0dB to

Output Signal swing

Each DAC input has an output range of 0.5 V_RMS/ 1.414 V_P-P

(Single-Ended) about a bias point equal to V_REFCAP(See Figure

<DAC_cct>)

-63dB in 1dB steps. Reading Control Register F and I will give

the highest ADC values for the left ADC and right ADC re-

spectively, since the bit was set. The ADC Peak registers are

automatically cleared after reading.

REFCAP

1.414 V

VOUT

P-P

820⍀

2n2F

NPO

Decimator Section

The digital decimation filter has a passband ripple of

0.002dB and a stopband attenuation of 120dB. The filter is

an FIR type with a linear phase response. The group delay at

48kHz is 910us. Output sample rates up to 48 kHz are sup-

ported.

Figure <DAC_cct>

–8–

REV.PrG

1...5 6 789 10 11...18

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