3 V, Parallel Input
Dual 12-Bit/10-Bit DACs
a
AD7396/AD7397
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Micropower: 100 A/DAC
0.1 A Typical Power Shutdown
Single Supply +2.7 V to +5.5 V Operation
Compact 1.1 mm Height TSSOP 24-Lead Package
AD7396: 12-Bit Resolution
AD7397: 10-Bit Resolution
0.9 LSB Differential Nonlinearity Error
V
V
DD
AD7396
12
DACA
REGISTER
12-BIT
DACA
LDA
OUTA
CS
INPUTA
REGISTER
A/B
12
1
V
DATA
REF
APPLICATIONS
INPUTB
REGISTER
Automotive Output Span Voltage
Portable Communications
Digitally Controlled Calibration
PC Peripherals
12
DACB
REGISTER
12-BIT
DACB
LDB
V
OUTB
AGND
DGND
RS
SHDN
GENERAL DESCRIPTION
Both parts are offered in the same pinout, allowing users to
The AD7396/AD7397 series of dual, 12-bit and 10-bit voltage-
output digital-to-analog converters are designed to operate from
a single +3 V supply. Built using a CBCMOS process, these
monolithic DACs offer the user low cost and ease of use in
single supply +3 V systems. Operation is guaranteed over the
supply voltage range of +2.7 V to +5.5 V, making this device
ideal for battery operated applications.
select the amount of resolution appropriate for their applications
without circuit card changes.
The AD7396/AD7397 are specified for operation over the ex-
tended industrial (–40°C to +85°C) temperature range. The
AD7397AR is specified for the –40°C to +125°C automotive
temperature range. AD7396/AD7397s are available in plastic
DIP, and 24-lead SOIC packages. The AD7397ARU is avail-
able for ultracompact applications in a thin 1.1 mm height
TSSOP 24-lead package.
A 12-bit wide data latch loads with a 45 ns write time allowing
interface to fast processors without wait states. The double
buffered input structure allows the user to load the input
registers one at a time, then a single load strobe tied to both
LDA+LDB inputs will simultaneously update both DAC out-
puts. LDA and LDB can also be independently activated to
immediately update their respective DAC registers. An address
input (A/B) decodes DACA or DACB when the chip select CS
input is strobed. Additionally, an asynchronous RS input sets
the output to zero-scale at power on or upon user demand.
Power shutdown to submicroamp levels is directly controlled by
the active low SHDN pin. While in the power shutdown state
register data can still be changed even though the output buffer
is in an open circuit state. Upon return to the normal operating
state the latest data loaded in the DAC register will establish the
output voltage.
1.0
V
V
= +3V
DD
0.8
0.6
0.4
= +2.5V
REF
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
T
= +25؇C, +85؇C, –55؇C
SUPERIMPOSED
A
0
512
1024 1536
2048
2560 3072
3584 4096
CODE – Decimal
Figure 1. DNL vs. Digital Code at Temperature
REV. 0
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© Analog Devices, Inc., 1998