Quad, Serial-Input
12-Bit/10-Bit DACs
AD7398/AD7399
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AD7398—12-bit resolution
V
V
B
V
A
DD
REF
REF
AD7399—10-bit resolution
AD7398/AD7399
Programmable power shutdown
Single (3 V to 5 V) or dual ( 5 V) supply operation
3-wire, serial SPI®-compatible interface
Internal power-on reset
Double buffered registers for simultaneous
multichannel DAC update
Four separate rail-to-rail reference inputs
Thin profile, TSSOP-16 package available
Low tempco: 1.5 ppm/°C
DAC A
REGISTER
INPUT
REG A
DAC A
DAC B
V
A
B
OUT
OUT
SERIAL
REGISTER
CS
SDI
DAC B
REGISTER
INPUT
REG B
V
DAC C
REGISTER
INPUT
REG C
V
V
C
D
DAC C
DAC D
OUT
CLK
Qualified for automotive applications
12/10
DAC D
REGISTER
APPLICATIONS
INPUT
REG D
OUT
Automotive output voltage span
Portable communications
Digitally controlled calibration
PC peripherals
POWER
ON RESET
V
RS
LDAC
V
C
V
D
GND
SS
REF
REF
Figure 1.
GENERAL DESCRIPTION
The AD7398/AD7399 family of quad, 12-bit/10-bit, voltage
output digital-to-analog converters (DACs) is designed to
operate from a single 3 V to 5 V supply or a dual 5 V supply.
Built with the Analog Devices, Inc. robust CBCMOS process,
these monolithic DACs offer the user low cost with ease-of-use
in single or dual-supply systems.
Both parts are offered in the same pinout, enabling users to
select the appropriate resolution for their application without
redesigning the layout. For 8-bit resolution applications, see the
pin-compatible AD7304 product.
The AD7398/AD7399 are specified over the extended industrial
(−40°C to +125°C) temperature range. Parts are available in
16-lead, wide body SOIC and ultracompact, thin, 1.1 mm
TSSOP packages.
The applied external reference, VREF, determines the full-scale
output voltage. Valid VREF values include VSS < VREF < VDD that
result in a wide selection of full-scale outputs. For multiplying
applications, ac inputs can be as large as 5 VP.
0.5
V
V
V
= +5V
= –5V
DD
SS
0.4
0.3
= +2.5V
REF
T
= 25°C
A
A doubled-buffered serial-data interface offers high speed, 3-wire,
SPI- and microcontroller-compatible inputs using serial data-in
0.2
CS
(SDI), clock (CLK), and a chip-select ( ). A common level-
0.1
LDAC
sensitive, load-DAC strobe ( ) input allows simultaneous
0
update of all DAC outputs from previously loaded input registers.
Additionally, an internal power-on reset forces the output voltage to
–0.1
–0.2
–0.3
–0.4
–0.5
RS
zero at system turn on. An external asynchronous reset ( ) also
forces all registers to the zero code state. A programmable power-
shutdown feature reduces power dissipation on unused DACs.
0
512
1024
1536
2048
2560
3072
3584
4096
CODE (Decimal)
Figure 2. AD7398 DNL vs. Code (TA = 25°C)
Rev. C
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