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AD7399

更新时间： 2024-11-18 23:16:19
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亚德诺 - ADI /
页数 文件大小 规格书
16页 272K
描述
Quad, Serial-Input 12-Bit/10-Bit DACs

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AD7399 数据手册

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Quad, Serial-Input  
12-Bit/10-Bit DACs  
a
AD7398/AD7399  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
AD7398—12-Bit Resolution  
AD7399—10-Bit Resolution  
V
V
B
V
A
DD  
REF  
REF  
Programmable Power Shutdown  
Single (3 V to 5 V) or Dual (؎5 V) Supply Operation  
3-Wire Serial SPI-Compatible Interface  
Internal Power ON Reset  
Double Buffered Registers for Simultaneous  
Multichannel DAC Update  
Four Separate Rail-to-Rail Reference Inputs  
Thin Profile TSSOP-16 Package Available  
Low Tempco 1.5 ppm/؇C  
DAC A  
INPUT  
REG A  
V
A
B
DAC A  
DAC B  
OUT  
OUT  
REGISTER  
SERIAL  
REGISTER  
DAC B  
REGISTER  
CS  
INPUT  
REG B  
V
SDI  
APPLICATIONS  
DAC C  
INPUT  
REG C  
V
V
C
DAC C  
DAC D  
Automotive Output Voltage Span  
Portable Communications  
Digitally Controlled Calibration  
PC Peripherals  
REGISTER  
OUT  
CLK  
DAC D  
REGISTER  
12/10  
INPUT  
REG D  
D
OUT  
GENERAL DESCRIPTION  
POWER  
ON RESET  
The AD7398/AD7399 family of quad, 12-bit/10-bit, voltage-  
output digital-to-analog converters is designed to operate from a  
single 3 V to 5 V or a dual 5 V supply. Built with Analog’s robust  
CBCMOS process, this monolithic DAC offers the user low  
cost, and ease-of-use in single or dual-supply systems.  
V
V
C
V
D
GND  
RS  
LDAC  
SS  
REF  
REF  
The applied external reference VREF determines the full-scale  
output voltage. Valid VREF values include VSS < VREF < VDD that  
result in a wide selection of full-scale outputs. For multiplying  
applications ac inputs can be as large as 5 VP.  
0.50  
0.40  
0.30  
0.20  
0.10  
A doubled-buffered serial-data interface offers high-speed,  
3-wire, SPI and microcontroller-compatible inputs using serial-  
data-in (SDI), clock (CLK), and a chip-select (CS). A common  
level-sensitive load-DAC strobe (LDAC) input allows simulta-  
neous update of all DAC outputs from previously loaded Input  
Registers. Additionally, an internal power ON reset forces the  
output voltage to zero at system turn ON. An external asynchro-  
nous reset (RS) also forces all registers to the zero code state. A  
programmable power-shutdown feature reduces power dissipa-  
tion on unused DACs.  
V
DD  
= +5V  
= –5V  
= +2.5V  
V
SS  
REF  
V
T
= 25؇C  
A
0
–0.10  
–0.20  
–0.30  
–0.40  
–0.50  
Both parts are offered in the same pinout to enable users to  
select the appropriate resolution for their application without  
redesigning the layout. For 8-bit resolution applications see the  
pin compatible AD7304 product.  
512  
4096  
1024  
1536  
CODE – Decimal  
2560  
3072 3584  
2048  
0
The AD7398/AD7399 is specified over the extended industrial  
(–40°C to +125°C) temperature range. Parts are available in  
wide body SOIC-16 and ultracompact thin 1.1 mm TSSOP-  
16 packages.  
Figure 1. AD7398 DNL vs. Code (TA = 25°C)  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2000  
1234567...16

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