+3 V, Dual, Serial Input
12-/10-Bit DACs
a
AD7394/AD7395
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Micropower: 100 A/DAC
V
V
DD
REF
0.1 A Typical Power Shutdown
Single-Supply +2.7 V to +5.5 V Operation
Compact 1.1 mm Height TSSOP-14 Package
AD7394/12-Bit Resolution
AD7395/10-Bit Resolution
Serial Interface with Schmitt Trigger Inputs
OP
AMP A
R
E
G
I
CS
D
A
C
EN
DAC A
V
OUTA
S
T
E
R
CLK
A
D
SDI
(DATA)
APPLICATIONS
R
E
G
I
S
T
E
R
P
R
S
H
I
F
T
12
Automotive Output Span Voltage
Portable Communications
Digitally Controlled Calibration
PC Peripherals
AD7394/AD7395
R
E
G
I
S
T
E
R
D
D
A
C
OP
AMP B
B
LDA
LDB
DAC B
V
OUTB
P
R
GENERAL DESCRIPTION
The AD7394/AD7395 family of dual, 12-/10-bit, voltage output
digital-to-analog converters is designed to operate from a single
+3 V supply. Built using a CBCMOS process, this monolithic
DAC offers the user low cost and ease of use in single-supply
+3 V systems. Operation is guaranteed over the supply voltage
range of +2.7 V to +5.5 V making this device ideal for battery
operated applications.
RS
DGND
MSB
AGND
SHDN
The AD7394/AD7395 is specified over the extended industrial
(–40°C to +85°C) temperature range. Packages available in-
clude plastic DIP and low profile 1.75 mm height SO-14 surface
mount packages. The AD7395ARU is available for ultracompact
applications in a thin 1.1 mm TSSOP-14 package. For automotive
applications the AD7395AR is specified for operation over the
(–40°C to +125°C) temperature range.
The full-scale output voltage is determined by the applied exter-
nal reference input voltage, VREF. The rail-to-rail VREF input
to VOUT outputs allows for a full-scale voltage set equal to the
positive supply VDD or any value in between.
A doubled-buffered serial data interface offers high speed,
microcontroller compatible inputs using serial-data-in (SDI),
clock (CLK) and load strobe (LDA + LDB) pins. A chip-select
(CS) pin simplifies connection of multiple DAC packages by
enabling the clock input when active low. Additionally, an RS
input sets the output to zero scale or to 1/2 scale based on the
logic level applied to the MSB pin. The power shutdown pin,
SHDN, reduces power dissipation to nanoamp current levels.
All digital inputs contain Schmitt-triggered logic levels to mini-
mize power dissipation and prevent false triggering on the clock
input.
1
V
V
= 3V
DD
0.8
0.6
= 2.5V
REF
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
Both parts are offered in the same pinout to allow users to select
the amount of resolution appropriate for their application with-
out circuit card redesign.
T
= –55؇C, +25؇C, +85؇C
SUPERIMPOSED
A
0
500
1000 1500
2000 2500 3000 3500 4000
CODE – Decimal
Figure 1. Differential Nonlinearity Error vs. Code
REV. 0
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© Analog Devices, Inc., 1998