AD7352YRUZ

更新时间： 2024-02-07 19:28:42

品牌	Logo	应用领域
亚德诺 - ADI		转换器模数转换器光电二极管
页数	文件大小	规格书
20页	498K
描述
Differential Input, Dual, Simultaneous Sampling, 3 MSPS, 12-Bit, SAR ADC

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技术参数
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AD7352YRUZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.28
Is Samacsys：	N	转换器类型：	ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	5 mm	最大线性误差 (EL)：	0.0244%
湿度敏感等级：	1	模拟输入通道数量：	1
位数：	12	功能数量：	2
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-40 °C	输出位码：	BINARY
输出格式：	SERIAL	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	2.5 V
认证状态：	Not Qualified	采样速率：	3 MHz
采样并保持/跟踪并保持：	TRACK	座面最大高度：	1.2 mm
子类别：	Analog to Digital Converters	标称供电电压：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	4.4 mm	Base Number Matches：	1

AD7352YRUZ 数据手册

AD7352

Alternatively, if the part is to be placed into full power-down

mode when the supplies are applied, three dummy cycles must

POWER-UP TIMES

The AD7352 has two power-down modes: partial power-down

and full power-down, which are described in detail in the

Normal Mode, Partial Power-Down Mode, and Full Power-

Down Mode sections. This section deals with the power-up

time required when coming out of any of these modes. Note

that the recommended decoupling capacitors must be in place

on the REF_Aand REF_Bpins for the power-up times to apply.

be initiated. The first dummy cycle must hold

low until after

the 10^thSCLK falling edge; the second and third dummy cycles

place the part into full power-down mode (see Figure 27 and

the Modes of Operation section).

POWER vs. THROUGHPUT RATE

The power consumption of the AD7352 varies with the

throughput rate. When using very slow throughput rates and

as fast an SCLK frequency as possible, the various power-down

options can be used to make significant power savings. However,

the AD7352 quiescent current is low enough that, even without

using the power-down options, there is a noticeable variation in

power consumption with sampling rate. This is true whether a

fixed SCLK value is used or it is scaled with the sampling

rate. Figure 29 shows a plot of power vs. throughput rate when

operating in normal mode for a fixed maximum SCLK frequency

and a SCLK frequency that scales with the sampling rate. The

internal reference was used for Figure 29.

To power up from partial power-down mode, one dummy cycle

is required. The device is fully powered up after approximately

333 ns have elapsed from the falling edge of . When the partial

power-up time has elapsed, the ADC is fully powered up, and

the input signal is acquired properly. The quiet time, t_QUIET

must still be allowed from the point where the bus goes back

into three-state after the dummy conversion to the next falling

edge of

To power up from full power-down mode, approximately

6 ms should be allowed from the falling edge of , shown

in Figure 28 as t_POWER-UP2

Note that during power-up from partial power-down mode, the

track-and-hold, which is in hold mode while the part is powered

down, returns to track mode after the first SCLK edge that the

part receives after the falling edge of

When power supplies are first applied to the AD7352, the ADC

can power up in either of the power-down modes or in normal

mode. Because of this, it is best to allow a dummy cycle to elapse

to ensure that the part is fully powered up before attempting a

valid conversion. Likewise, if the part is to be kept in partial

power-down mode immediately after the supplies are applied,

80MHz SCLK

VARIABLE SCLK

then two dummy cycles must be initiated. The first dummy

cycle must hold

low until after the 10 SCLK falling edge; in

1000

2000

3000

the second cycle,

must be brought high between the second

and 10^thSCLK falling edges (see Figure 25).

THROUGHPUT (kSPS)

Figure 29. Power vs. Throughput Rate

Rev. 0 | Page 17 of 20

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与AD7352YRUZ相关器件

型号	品牌	描述	获取价格	数据表
AD7352YRUZ-500RL7	ADI	Differential Input, Dual, Simultaneous Sampling, 3 MSPS, 12-Bit, SAR ADC	获取价格
AD7352YRUZ-REEL	ADI	IC 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16, MO-153AB, TSSOP-16, An	获取价格
AD7352YRUZ-REEL7	ADI	IC 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16, MO-153AB, TSSOP-16, An	获取价格
AD7352YRUZ-RL	ADI	Differential Input, Dual, Simultaneous Sampling, 3 MSPS, 12-Bit, SAR ADC	获取价格
AD7356	ADI	Differential Input, Dual, 5 MSPS, 12-Bit, SAR ADC	获取价格
AD7356_08	ADI	Differential Input, Dual, Simultaneous Sampling, 5 MSPS, 12-Bit, SAR ADC	获取价格

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