Six-InputChannel
AnalogFrontEnd
a
PreliminaryTechnicalData
AD73560
FEATURES
F UNC T IO NAL BLO C K D IAG RAM
AFE PERFORMANCE
Six 16-Bit A/ D Converters
Program m able Input Sam ple Rate
Sim ultaneous Sam pling
76 dB SNR
64 kS/ s Maxim um Sam ple Rate
–83 dB Crosstalk
Low Group Delay (25 m s Typ per ADC Channel)
Program m able Input Gain
Single Supply Operation
On-Chip Reference
POWER-DOWN
CONTROL
MEMORY
DATA ADDRESS
GENERATORS
PROGRAMMABLE
I/O
AND
PROGRAM
SEQUENCER
16K PM
(OPTIONAL 8K)
16K DM
(OPTIONAL 8K)
FULL MEMORY
MODE
DAG
2
DAG
1
FLAGS
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
EXTERNAL
DATA
BUS
PROGRAM MEMORY DATA
DATA MEMORY DATA
BYTE DMA
CONTROLLER
FLASH
Byte Memory
64 kbytes
SERIAL PORTS
ARITHMETIC UNITS
TIMER
ALU
SHIFTER
MAC
SPORT
0
SPORT 1
ADSP-2100 BASE
ARCHITECTURE
DSP PERFORMANCE
SERIAL PORT
19ns Instruction Cycle Tim e @3.3 V, 52 MIPS
Sustained Perform ance
REF
SPO RT
2
Single-Cycle Instruction Execution
Single-Cycle Context Sw itch
ADC1
AD C2
ADC3
ADC4
AD C5
AD C6
3-Bus Architecture Allow s Dual Operand Fetches in
Every Instruction Cycle
ANALO G FRO NT END
SECTION
Multifunction Instructions
Pow er-Dow n Mode Featuring Low CMOS Standby
Pow er Dissipation w ith 400 Cycle Recovery from
Pow er-Dow n Condition
An on-chip reference voltage of 2.5V is included. T he
sampling rate of the device is programmable with four
separate settings offering 64 kHz, 32 kHz, 16 kHz and 8
kHz sampling rates (from a master clock of 16.384 MHz)
while the serial port (SPORT 2) allows easy expansion of
the number of input channels by cascading extra AFE
external to the AD73560.
Low Pow er Dissipation in Idle Mode
FLASH MEMORY
64Kbytes
T he AD73560’s DSP engine combines the ADSP-2100
family base architecture (three computational units, data
address generators and a program sequencer) with two
serial ports, a 16-bit internal DMA port, a byte DMA
port, a programmable timer, Flag I/O, extensive interrupt
capabilities and on-chip program and data memory.
T he AD73560-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM and
16 K (16-bit) of data RAM. T he AD73560-40 integrates
40K bytes of on-chip memory configured as 8K words
(24-bit) of program RAM and 8K (16-bit) of data RAM.
Power-down circuitry is also provided to meet the low
power needs of battery operated portable equipment. T he
AD73560 is available in a 119-ball PBGA package.
Writable in pages of 128 bytes
Fast Page Write Cycle of 5m s (typical)
G E NE R AL D E S C R IP T IO N
T he AD73560 is a six-input channel analog front-end
processor for general purpose applications including in-
dustrial power metering or multichannel analog inputs. It
features six 16-bit A/D conversion channels each of which
provide 76 dB signal-to-noise ratio over a DC to 4KHz
signal bandwidth. Each channel also features a program-
mable input gain amplifier (PGA) with gain settings in
eight stages from 0 dB to 38 dB.
T he AD73560 is particularly suitable for industrial power
metering as each channel samples synchronously, ensuring
that there is no (phase) delay between the conversions.
T he AD73560 also features low group delay conversions
on all channels.
REV. PrA
8/99
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
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Tel: 781/329-4700
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© Analog Devices, Inc., 1999