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AD73360LARZ-REEL7 PDF预览

AD73360LARZ-REEL7

更新时间： 2024-02-20 06:13:09
品牌 Logo 应用领域
亚德诺 - ADI 电信光电二极管电信集成电路
页数 文件大小 规格书
32页 266K
描述
IC SPECIALTY TELECOM CIRCUIT, PDSO28, SOIC-28, Telecom IC:Other

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AD73360LARZ-REEL7 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：28
Reach Compliance Code：unknown风险等级：5.89
JESD-30 代码：R-PDSO-G28JESD-609代码：e0
长度：17.9 mm湿度敏感等级：NOT SPECIFIED
功能数量：1端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：220认证状态：COMMERCIAL
座面最大高度：2.65 mm标称供电电压：3.3 V
表面贴装：YES电信集成电路类型：TELECOM CIRCUIT
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mm

AD73360LARZ-REEL7 数据手册

 浏览型号AD73360LARZ-REEL7的Datasheet PDF文件第5页浏览型号AD73360LARZ-REEL7的Datasheet PDF文件第6页浏览型号AD73360LARZ-REEL7的Datasheet PDF文件第7页浏览型号AD73360LARZ-REEL7的Datasheet PDF文件第9页浏览型号AD73360LARZ-REEL7的Datasheet PDF文件第10页浏览型号AD73360LARZ-REEL7的Datasheet PDF文件第11页 
AD73360L  
FUNCTIONAL DESCRIPTION  
Analog Sigma-Delta Modulator  
General Description  
The AD73360L input channels employ a sigma-delta conver-  
sion technique, which provides a high resolution 16-bit output  
with system filtering being implemented on-chip.  
The AD73360L is a six-input channel, 16-bit, analog front end.  
It comprises six independent encoder channels each featuring  
signal conditioning, programmable gain amplifier, sigma-delta  
A/D converter and decimator sections. Each of these sections is  
described in further detail below.  
Sigma-delta converters employ a technique known as over-  
sampling, where the sampling rate is many times the highest  
frequency of interest. In the case of the AD73360L, the initial  
sampling rate of the sigma-delta modulator is DMCLK/8. The  
main effect of oversampling is that the quantization noise is  
spread over a very wide bandwidth, up to fS/2 = DMCLK/16  
(Figure 6a). This means that the noise in the band of interest is  
much reduced. Another complementary feature of sigma-delta  
converters is the use of a technique called noise-shaping. This  
technique has the effect of pushing the noise from the band of  
interest to an out-of-band position (Figure 6b). The combina-  
tion of these techniques, followed by the application of a digital  
filter, reduces the noise in band sufficiently to ensure good  
dynamic performance from the part (Figure 6c).  
Encoder Channel  
Each encoder channel consists of a signal conditioner, a switched  
capacitor PGA, and a sigma-delta analog-to-digital converter  
(ADC). An on-board digital filter, which forms part of the  
sigma-delta ADC, also performs critical system-level filtering.  
Due to the high-level of oversampling, the input antialias require-  
ments are reduced such that a simple single pole RC stage is  
sufficient to give adequate attenuation in the band of interest.  
Signal Conditioner  
Each analog channel has an independent signal conditioning  
block. This allows the analog input to be configured by the user  
depending on whether differential or single-ended mode is used.  
Programmable Gain Amplifier  
Each encoder section’s analog front end comprises a switched  
capacitor PGA that also forms part of the sigma-delta modula-  
tor. The SC sampling frequency is DMCLK/8. The PGA,  
whose programmable gain settings are shown in Table II, may  
be used to increase the signal level applied to the ADC from  
low-output sources such as microphones, and can be used to  
avoid placing external amplifiers in the circuit. The input signal  
level to the sigma-delta modulator should not exceed the maxi-  
mum input voltage permitted.  
BAND  
f
/2  
S
OF  
DMCLK/16  
INTEREST  
a.  
The PGA gain is set by bits IGS0, IGS1, and IGS2 in control  
Registers D, E, and F.  
NOISE-SHAPING  
Table II. PGA Settings for the Encoder Channel  
BAND  
OF  
INTEREST  
f
/2  
S
IxGS2  
IxGS1  
IxGS0  
Gain (dB)  
DMCLK/16  
b.  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
6
12  
18  
20  
26  
32  
38  
DIGITAL FILTER  
BAND  
OF  
INTEREST  
f
/2  
S
DMCLK/16  
ADC  
c.  
Each channel has its own ADC consisting of an analog sigma-  
delta modulator and a digital antialiasing decimation filter. The  
sigma-delta modulator noise-shapes the signal and produces  
1-bit samples at a DMCLK/8 rate. This bitstream, representing  
the analog input signal, is input to the antialiasing decimation  
filter. The decimation filter reduces the sample rate and increases  
the resolution.  
Figure 6. Sigma-Delta Noise Reduction  
–8–  
REV. 0  
1...567891011...32

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