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AD73360LARZ-REEL7 PDF预览

AD73360LARZ-REEL7

更新时间: 2024-02-02 04:27:59
品牌 Logo 应用领域
亚德诺 - ADI 电信光电二极管电信集成电路
页数 文件大小 规格书
32页 266K
描述
IC SPECIALTY TELECOM CIRCUIT, PDSO28, SOIC-28, Telecom IC:Other

AD73360LARZ-REEL7 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:28
Reach Compliance Code:unknown风险等级:5.89
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:17.9 mm湿度敏感等级:NOT SPECIFIED
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):220认证状态:COMMERCIAL
座面最大高度:2.65 mm标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mm

AD73360LARZ-REEL7 数据手册

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AD73360L  
TERMINOLOGY  
ABBREVIATIONS  
Absolute Gain  
ADC  
Analog-to-Digital Converter.  
Absolute gain is a measure of converter gain for a known signal.  
Absolute gain is measured (differentially) with a 1 kHz sine  
wave at 0 dBm0 for each ADC. The absolute gain specification  
is used for gain tracking error specification.  
BW  
Bandwidth.  
CRx  
A Control Register where x is a placeholder for  
an alphabetic character (AE). There are eight  
read/write control registers on the AD73360L—  
designated CRA through CRE.  
Crosstalk  
Crosstalk is due to coupling of signals from a given channel to  
an adjacent channel. It is defined as the ratio of the amplitude of  
the coupled signal to the amplitude of the input signal. Crosstalk  
is expressed in dB.  
CRx:n  
A bit position, where n is a placeholder for a  
numeric character (07), within a control regis-  
ter; where x is a placeholder for an alphabetic  
character (AE). Position 7 represents the MSB  
and Position 0 represents the LSB.  
Gain Tracking Error  
Gain tracking error measures changes in converter output for  
different signal levels relative to an absolute signal level. The  
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz  
for each ADC. Gain tracking error at 0 dBm0 (ADC) is 0 dB by  
definition.  
DMCLK  
FSLB  
Device (Internal) Master Clock. This is the  
internal master clock resulting from the external  
master clock (MCLK) being divided by the on-  
chip master clock divider.  
Frame Sync Loop-Backwhere the SDOFS of  
the final device in a cascade is connected to the  
RFS and TFS of the DSP and the SDIFS of first  
device in the cascade. Data input and output  
occur simultaneously. In the case of non-FSLB,  
SDOFS and SDO are connected to the Rx Port  
of the DSP while SDIFS and SDI are connected  
to the Tx Port.  
Group Delay  
Group delay is defined as the derivative of radian phase with  
respect to radian frequency, dø(f)/df. Group delay is a measure  
of average delay of a system as a function of frequency. A linear  
system with a constant group delay has a linear phase response.  
The deviation of group delay from a constant indicates the  
degree of nonlinear phase response of the system.  
Idle Channel Noise  
PGA  
SC  
Programmable Gain Amplifier.  
Switched Capacitor.  
Signal-to-Noise Ratio.  
Serial Port.  
Idle channel noise is defined as the total signal energy measured  
at the output of the device when the input is grounded (mea-  
sured in the frequency range 0 Hz4 kHz).  
SNR  
SPORT  
THD  
VBW  
Intermodulation Distortion  
With inputs consisting of sine waves at two frequencies, fa and  
fb, any active device with nonlinearities will create distortion  
products at sum and difference frequencies of mfa nfb where  
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which  
neither m nor n are equal to zero. For final testing, the second  
order terms include (fa + fb) and (fa fb), while the third order  
terms include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb).  
Total Harmonic Distortion.  
Voice Bandwidth.  
Power Supply Rejection  
Power supply rejection measures the susceptibility of a device to  
noise on the power supply. Power supply rejection is measured  
by modulating the power supply with a sine wave and measuring  
the noise at the output (relative to 0 dB).  
Sample Rate  
The sample rate is the rate at which each ADC updates its output  
register. It is set relative to the DMCLK and the programmable  
sample rate setting.  
SNR + THD  
Signal-to-noise ratio plus harmonic distortion is defined to be  
the ratio of the rms value of the measured input signal to the  
rms sum of all other spectral components in a given frequency  
range, including harmonics but excluding dc.  
–7–  
REV. 0  

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