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AD7265BCP

更新时间： 2024-02-28 02:05:05
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 转换器
页数 文件大小 规格书
29页 1593K
描述
DUAL 3-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, QCC32, LEAD FREE, MO-220-VHHD-2, LFCSP-32

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AD7265BCP 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：32
Reach Compliance Code：unknown风险等级：5.38
最大模拟输入电压：5.25 V最小模拟输入电压：
最长转换时间：0.875 µs转换器类型：ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：S-XQCC-N32JESD-609代码：e0
长度：5 mm最大线性误差 (EL)：0.0244%
湿度敏感等级：3模拟输入通道数量：3
位数：12功能数量：2
端子数量：32最高工作温度：125 °C
最低工作温度：-40 °C输出位码：BINARY, 2'S COMPLEMENT BINARY
输出格式：SERIAL封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：240
采样速率：1 MHz采样并保持/跟踪并保持：TRACK
座面最大高度：1 mm标称供电电压：3 V
表面贴装：YES温度等级：AUTOMOTIVE
端子面层：TIN LEAD端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：5 mm
Base Number Matches：1

AD7265BCP 数据手册

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AD7265  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
DGND  
A1  
A2  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
DGND  
REF SELECT  
A1  
A2  
SGL/DIFF  
RANGE  
PIN 1  
PIN 1  
REF SELECT  
INDICATOR  
AV  
DD  
SGL/DIFF  
RANGE  
AV  
DD  
A
D
A
CAP  
AD7265  
TOP VIEW  
(Not to Scale)  
AD7265  
TOP VIEW  
(Not to Scale)  
D
AGND  
AGND  
D
B
CAP  
CAP  
AGND  
D
B
AGND  
CAP  
V
V
V
V
A1  
A2  
B1  
B2  
AGND  
AGND  
V
V
B1  
A1  
V
V
B2  
A2  
9
10 11 12 13 14 15 16  
Figure 3. 32-Lead SU-32-2  
Figure 2. 32-Lead CP-32-2  
Table 4. Pin Function Descriptions  
Pin No. Mnemonic Description  
1, 29  
DGND  
Digital Ground. This is the ground reference point for all digital circuitry on the AD7265. Both DGND pins should  
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential  
and must not be more than 0.3 V apart, even on a transient basis.  
2
REF SELECT  
Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used  
as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to  
decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the  
AD7265 through the DCAPA pin and/or the DCAPB pin.  
3
AVDD  
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7265. The  
AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a  
transient basis. This supply should be decoupled to AGND.  
4, 20  
DCAPA, DCAP  
AGND  
B
Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to  
decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference  
can be taken from these pins and applied externally to the rest of a system. The range of the external reference is  
dependent on the analog input range selected.  
Analog Ground. Ground reference point for all analog circuitry on the AD7265. All analog input signals and any  
external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect  
to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must  
not be more than 0.3 V apart, even on a transient basis.  
5, 6, 19  
7 to 12  
VA1 to VA6  
Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential  
analog input channel pairs. See Table 6.  
13 to 18 VB6 to VB1  
Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential  
analog input channel pairs. See Table 6.  
21  
22  
RANGE  
Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog  
input channels. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin is tied to a logic  
high when CS goes low, the analog input range is 2 × VREF. See the Analog Input Selection section for details.  
SGL/DIFF  
Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A  
logic low selects differential operation while a logic high selects single-ended operation. See the Analog Input  
Selection section for details.  
23 to 25 A2 to A0  
Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously  
converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair  
of channels selected may be two single-ended channels or two differential pairs. The logic states of these pins  
need to be set up prior to the acquisition time and subsequent falling edge of CS to correctly set up the  
multiplexer for that conversion. See the Analog Input Selection section for further details and Table 6 for  
multiplexer address decoding.  
26  
27  
CS  
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7265  
and framing the serial data transfer.  
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7265. This  
clock is also used as the clock source for the conversion process.  
SCLK  
Rev. A | Page 7 of 28  
 
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