AD7150
Preliminary Technical Data
ARCHITECTURE AND MAIN FEATURES
+3.3V
V
DD
CLOCK
GENERATOR
PWR DOWN
TIMER
AD7150
C
IN1
C
SENS1
SCL
DIGITAL
FILTER
SERIAL
INTERFACE
PROGRAMMING
INTERFACE
Σ−∆ CDC
SDA
EXC1
MUX
OUT1
C
IN2
THRESHOLD
CAP DAC
C
SENS2
DIGITAL
OUTPUTS
OUT2
EXCITATION
THRESHOLD
GND
EXC2
Figure 10. AD7150 Block Diagram
OVERVIEW
The AD7150 core is a high performance capacitance to digital
converter (CDC), which allows the part to be interfaced directly
to a capacitive sensor.
CAPACITANCE TO DIGITAL CONVERTER
(CDC)
The comparators compare the CDC result with thresholds,
either fixed or dynamically adjusted by the on-chip adaptive
threshold algorithm engine. Thus, the outputs indicate a
defined change in the input sensor capacitance.
CLOCK
GENERATOR
0x000 .. 0xFFF
DATA
CIN
Σ-∆
MODULATOR
DIGITAL
FILTER
C
SENS
0..4pF
The AD7150 also integrates an excitation source and CAPDAC
for the capacitive inputs, an input multiplexer, a complete clock
generator, a power down timer, control logic, and an I2C-
compatible serial interface for configuring the part and
accessing the internal CDC data, status, etc., if required in the
system. See Figure 10.
EXC
EXCITATION
Figure 11. CDC Simplified Block Diagram
CAPDAC
CAPACITANCE TO DIGITAL CONVERTER
The AD7150 CDC core maximum full-scale input range is 4 pF.
However, the part can accept a higher capacitance on the input
and the offset (not-changing component) capacitance up to 10
pF can be balanced by a programmable on-chip CAPDAC.
Figure 11 shows the CDC simplified functional diagram. The
converter consists of a second order Σ-Δ (or charge balancing)
modulator and a third order digital filter. The measured
capacitance CX is connected between an excitation source and
the Σ-Δ modulator input. The excitation signal is applied on the
CX during the conversion and the modulator continuously
samples the charge going through the CX. The digital filter
processes the modulator output, which is a stream of 0s and 1s
containing the information in 0 and 1 density. The data are
processed by the adaptive threshold engine and output
comparators; the data can be also read through the serial
interface.
CAPDAC
10pF
0x000 .. 0xFFF
CIN(+)
EXC
0..4pF
CDC
DATA
C
SENS
10..14pF
Figure 12. Using CAPDAC
The AD7150 is designed for floating capacitive sensors.
Therefore, both CX plates have to be isolated from ground or
any other fixed potential node in the system.
The CAPDAC can be understood as a negative capacitance
connected internally to the CIN pin. The CAPDAC has a 6-bit
resolution and a monotonic transfer function. The example in
Figure 12 shows how to use the CAPDAC to shift the CDC 4 pF
input range to measure capacitance between 10 pF to 14 pF.
The AD7150 features slew rate limiting on the excitation voltage
output, which decrease the energy of higher harmonics on the
excitation signal and dramatically improves the system EMC
radiation performance.
Rev. PrD | Page 8 of 24