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AD7134

更新时间： 2024-09-29 14:57:55
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亚德诺 - ADI /
页数 文件大小 规格书
86页 1483K
描述
24 位 4 通道同步采样 1.5 MSPS 精密无偏置 ADC

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AD7134 数据手册

 浏览型号AD7134的Datasheet PDF文件第2页浏览型号AD7134的Datasheet PDF文件第3页浏览型号AD7134的Datasheet PDF文件第4页浏览型号AD7134的Datasheet PDF文件第5页浏览型号AD7134的Datasheet PDF文件第6页浏览型号AD7134的Datasheet PDF文件第7页 
24-Bit, 4-Channel Simultaneous Sampling  
1.5 MSPS Precision Alias Free ADC  
AD7134  
Data Sheet  
Sinc3 filter with 50 Hz/60 Hz rejection  
FEATURES  
Crosstalk: 130.7 dBFS  
Daisy-chaining  
Alias free: inherent antialias rejection high performance  
mode 102.5 dB, typical  
CRC error checking on data and SPI interface  
Two power modes: high performance mode and low power  
mode  
Power supply: 4.5 V to 5.5 V and 1.65 V to 1.95 V  
1.8 V IOVDD level  
Excellent ac and dc performance  
108 dB dynamic range at ODR = 374 kSPS, FIR filter, typical  
137 dB dynamic range at ODR = 10 SPS, sinc3 filter, typical  
THD: −120 dB typical with 1 kHz input tone  
Offset error drift: 0.7 µV/°C typical  
External reference: 4.096 V or 5 V  
Gain drift: 2 ppm/°C typical  
Crystal or external CMOS clock of 48 MHz  
SPI or pin (standalone) configurable operation  
Operating temperature range: 0°C to 85°C  
Available in 8 mm × 8 mm, 56-lead LFCSP with exposed pad  
INL: 2 ppm of FSR typical  
Dynamic range enhancement: 4:1 and 2:1 averaging mode  
126 dB, A weighted dynamic range  
Resistive ADC and reference input  
Easy to sync: asynchronous sample rate converter  
Multidevice synchronization with one signal line  
Programmable data rates from 0.01 kSPS to 1496 kSPS  
with resolution of 0.01 SPS  
Option to control output data rate by external signal  
Linear phase digital filter options  
Low ripple FIR filter: 32 µdB pass-band ripple, dc to  
161.942 kHz  
Low latency sinc3 filter and sinc6 filter, dc to 391.5 kHz  
APPLICATIONS  
Electrical test and measurement  
Audio test  
3-phase power quality analysis  
Control and hardware in loop verification  
Sonars  
Condition monitoring for predictive maintenance  
Acoustic and material science research and development  
FUNCTIONAL BLOCK DIAGRAM  
FORMAT0/CS  
FORMAT1/SCLK  
DEC1/DCLKMODE  
DEC0/DCLKIO  
DEC2/SDI  
MODULATOR  
CLOCK  
VCM  
REFERENCE  
MANAGEMENT  
1/2  
LDO  
LDOIN  
MCLK  
ODR  
ASYNCHRONOUS  
SAMPLE RATE  
CONVERTER  
AIN0+  
AIN0–  
CTSD  
MODULATOR  
PROGRAMMABLE  
DIGITAL FILTER  
DEC3/SDO  
DCLK  
ODR  
ASYNCHRONOUS  
SAMPLE RATE  
CONVERTER  
AIN1+  
AIN1–  
CTSD  
DIGITAL  
PROGRAMMABLE  
DIGITAL FILTER  
MODULATOR  
INTERFACE  
DOUT0  
DOUT1  
LOGIC  
DOUT2  
ASYNCHRONOUS  
SAMPLE RATE  
CONVERTER  
AIN2+  
AIN2–  
CTSD  
MODULATOR  
PROGRAMMABLE  
DIGITAL FILTER  
DIAGNOSTIC  
DOUT3  
PIN/SPI  
MODE  
ASYNCHRONOUS  
SAMPLE RATE  
CONVERTER  
AIN3+  
AIN3–  
CTSD  
PROGRAMMABLE  
DIGITAL FILTER  
DCLKRATE0/GPIO0  
DCLKRATE1/GPIO1  
DCLKRATE2/GPIO2  
PWRMODE/GPIO3  
FILTER0/GPIO4  
FILTER1/GPIO5  
FRAME0/GPIO6  
FRAME1/GPIO7  
MODULATOR  
POWER MANAGEMENT  
AGND1V8  
DGND1V8  
CLKGND  
AD7134  
LDO  
LDO  
Figure 1.  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2020 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
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