Datasheet > AD698APZ

AD698APZ

更新时间： 2024-01-28 13:09:14

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
12页	235K
描述
Universal LVDT Signal Conditioner

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技术参数
数据手册
替代型号

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AD698APZ 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	24
Reach Compliance Code：	unknown	风险等级：	5.88
最大模拟输入电压：	3.5 V	转换器类型：	SIGNAL CONDITIONER
JESD-30 代码：	R-GDIP-T24	JESD-609代码：	e0
湿度敏感等级：	NOT APPLICABLE	最大负电源电压：	-18 V
最小负电源电压：	-6.5 V	标称负供电电压：	-15 V
功能数量：	1	端子数量：	24
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT APPLICABLE	认证状态：	COMMERCIAL
座面最大高度：	5.08 mm	信号/输出频率：	20000 Hz
最大供电电压：	18 V	最小供电电压：	6.5 V
标称供电电压：	15 V	表面贴装：	NO
温度等级：	MILITARY	端子面层：	TIN LEAD
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	15.24 mm	Base Number Matches：	1

AD698APZ 数据手册

AD698

Multiply the primary excitation voltage by the VT R to get

the expected secondary voltage at mechanical full scale. For

example, for an LVDT with a sensitivity of 2.4 mV/V/mil and

a full scale of ±0.1 inch, the VT R = 0.0024 V/V/Mil × 100

mil = 0.24. Assuming the maximum excitation of 3.5 V rms,

the maximum secondary voltage will be 3.5 V rms × 0.24 =

0.84 V rms, which is in the acceptable range.

b. Full-scale core displacement from null, d

S × d = VT R and also equals the ratio A/B at mechanical full

scale. T he VT R should be converted to units of V/V.

For a full-scale displacement of d inches, voltage out of the

AD698 is computed as

V_OUT= S × d × 500 µA × R2

Conversely the VT R may be measured explicitly. With the

LVDT energized at its typical drive level V_PRI, as indicated

by the manufacturer, set the core displacement to its me-

chanical full-scale position and measure the output V_SECof

the secondary. Compute the LVDT voltage transformation

ratio, VT R. VTR = V_SEC//VPRI. For the E100, V_SEC= 0.72 V

for V_PRI= 3 V. VT R = 0.24.

V_OUTis measured with respect to the signal reference,

Pin 21, shown in Figure 7.

Solving for R2,

V_OUT

S × d × 500 µA

R2 =

(1)

For V_OUT= ±10 V full-scale range (20 V span) and d = ±0.1

inch full-scale displacement (0.2 inch span)

For situations where LVDT sensitivity is low, or the me-

chanical FS is a small fraction of the total stroke length, an

input excitation of more than 3.5 V rms may be needed. In

this case a voltage divider network may be placed across the

LVDT primary to provide smaller voltage for the +BIN and

–BIN input. If, for example, a network was added to divide

the B Channel input by 1/2, then the VT R should also be re-

duced by 1/2 for the purpose of component selection.

20V

R2 =

= 83. 3 kΩ

2. 4 × 0.2 × 500 µA

V_OUTas a function of displacement for the above example is

shown in Figure 10.

V_OUT(VOLTS)

Check the power supply voltages by verifying that the peak

values of V_Aand V_Bare at least 2.5 volts less than the volt-

ages at +V_Sand –V_S.

+10

+0.1d (INCHES)

–0.1

6. Referring to Figure 9, for V_S= ±15 V, select the value of the

amplitude determining component R1 as shown by the curve

in Figure 9.

–10

Figure 10. V_OUT(±10 V Full Scale) vs. Core Displace-

m ent (±0.1 Inch)

E. O ptional O ffset of O utput Voltage Swing

9. Selections of R3 and R4 permit a positive or negative output

voltage offset adjustment.

V_OS= 1. 2 V × R2 ×

–

(2)

R3 + 2 kΩ

+ 2 kΩ

V rms

For no offset adjustment R3 and R4 should be open circuit.

T o design a circuit producing a 0 V to +10 V output for a

displacement of +0.1 inch, set V_OUTto +10 V, d = 0.2 inch

and solve Equation (1) for R2.

(VOLTS)

OUT

0.01

0.1

100

R1 – kΩ

+0.1d (INCHES)

–0.1

Figure 9. Excitation Voltage V_EXCvs. R1

–5

7. C2, C3 and C4 are a function of the desired bandwidth of

the AD698 position measurement subsystem. T hey should

be nominally equal values.

Figure 11. V_OUT(±5 V Full Scale) vs. Core Displacem ent

(±0.1 Inch)

C2 = C3 = C4 = 10^–4Farad Hz/f_5UBSYSTEM(Hz)

If the desired system bandwidth is 250 Hz, then

C2 = C3 = C4 = 10^-4Farad Hz/250 Hz = 0.4 µF

T his will produce a response shown in Figure 11.

In Equation (2) set V_OS= 5 V and solve for R3 and R4. Since a

positive offset is desired, let R4 be open circuit. Rearranging

Equation (2) and solving for R3

See Figures 14, 15 and 16 for more information about

AD698 bandwidth and phase characterization.

1. 2 × R2

V_OS

R3 =

– 2 kΩ = 7.02 kΩ

D . Set the Full-Scale O utput Voltage

8. T o compute R2, which sets the AD698 gain or full-scale

output range, several pieces of information are needed:

a. LVDT sensitivity, S

REV. B

–7–

1...4 5 678 9 10...12

中文翻译

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AD698APZ 替代型号

型号	品牌	替代类型	描述	数据表
AD698AP	ADI	类似代替	Universal LVDT Signal Conditioner

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