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AD6655ABCPZ-105 PDF预览

AD6655ABCPZ-105

更新时间: 2024-01-09 14:16:52
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亚德诺 - ADI /
页数 文件大小 规格书
85页 2138K
描述
IF Diversity Receiver

AD6655ABCPZ-105 数据手册

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IF Diversity Receiver  
AD6655  
Data Sheet  
FEATURES  
APPLICATIONS  
SNR = 74.5 dBc (75.5 dBFS) in a 32.7 MHz BW at  
70 MHz at 150 MSPS  
Communications  
Diversity radio systems  
SFDR = 80 dBc to 70 MHz at 150 MSPS  
1.8 V analog supply operation  
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS  
output supply  
Integer 1-to-8 input clock divider  
Integrated dual-channel ADC  
Sample rates up to 150 MSPS  
Multimode digital receivers (3G)  
TD-SCDMA, WiMax, WCDMA,  
CDMA2000, GSM, EDGE, LTE  
I/Q demodulation systems  
Smart antenna systems  
General-purpose software radios  
Broadband data applications  
IF sampling frequencies to 450 MHz  
Internal ADC voltage reference  
PRODUCT HIGHLIGHTS  
Integrated ADC sample-and-hold inputs  
Flexible analog input range: 1 V p-p to 2 V p-p  
ADC clock duty cycle stabilizer  
1. Integrated dual, 14-bit, 150 MSPS ADC.  
2. Integrated wideband decimation filter and 32-bit  
complex NCO.  
95 dB channel isolation/crosstalk  
Integrated wideband digital downconverter (DDC)  
32-bit complex, numerically controlled oscillator (NCO)  
Decimating half-band filter and FIR filter  
Supports real and complex output modes  
Fast attack/threshold detect bits  
Composite signal monitor  
3. Fast overrange detect and signal monitor with serial output.  
4. Proprietary differential input maintains excellent SNR  
performance for input frequencies up to 450 MHz.  
5. Flexible output modes, including independent CMOS,  
interleaved CMOS, IQ mode CMOS, and interleaved LVDS.  
6. SYNC input allows synchronization of multiple devices.  
7. 3-bit SPI port for register programming and register readback.  
Energy-saving power-down modes  
FUNCTIONAL BLOCK DIAGRAM  
AVDD  
FD[0:3]A  
DVDD  
DRVDD  
FD BITS/THRESHOLD  
DETECT  
AD6655  
I
VIN+A  
VIN–A  
D13A  
D0A  
LP/HP  
DECIMATING  
HB FILTER +  
FIR  
SHA  
ADC  
Q
CLK+  
CLK–  
VREF  
DIVIDE 1  
TO 8  
32-BIT  
TUNING  
NCO  
SENSE  
SIGNAL  
MONITOR  
fADC/8  
NCO  
DUTY  
CYCLE  
STABILIZER  
DCOA  
DCOB  
DCO  
GENERATION  
CML  
REF  
SELECT  
RBIAS  
Q
I
LP/HP  
DECIMATING  
HB FILTER +  
FIR  
D13B  
D0B  
VIN–B  
VIN+B  
SHA  
ADC  
PROGRAMMING DATA  
SPI  
MULTI-CHIP  
SYNC  
FD BITS/THRESHOLD SIGNAL MONITOR  
SIGNAL MONITOR  
INTERFACE  
DETECT  
DATA  
AGND  
SYNC  
FD[0:3]B  
SMI  
SMI  
SMI  
SDIO/ SCLK/ CSB DRGND  
DCS DFS  
SDFS SCLK/ SDO/  
PDWN OEB  
NOTES  
1.PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 10 FOR LVDS PIN NAMES.  
Figure 1.  
Rev. B  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2007–2014 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 

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