Datasheet > AD6600AST

AD6600AST

更新时间： 2024-02-24 02:40:05

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		转换器
页数	文件大小	规格书
25页	988K
描述
2-CH 11-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44, PLASTIC, LQFP-44

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AD6600AST 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LQFP,	针数：	44
Reach Compliance Code：	unknown	风险等级：	5.41
Is Samacsys：	N	转换器类型：	ADC, PROPRIETARY METHOD
JESD-30 代码：	S-PQFP-G44	JESD-609代码：	e0
长度：	10 mm	湿度敏感等级：	3
模拟输入通道数量：	2	位数：	11
功能数量：	1	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出位码：	2'S COMPLEMENT BINARY	输出格式：	PARALLEL, WORD
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	240	采样速率：	20 MHz
采样并保持/跟踪并保持：	TRACK	座面最大高度：	1.6 mm
标称供电电压：	5 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	10 mm	Base Number Matches：	1

AD6600AST 数据手册

AD6600

AVCC

So for settling purposes, with 13 MSPS encode and 50% duty

cycle, the maximum allowable capacitance for proper settling is

RESONANT

FILTER PORT

_TOTAL= 13.6 pF.

315ꢁ

As stated above, this C_TOTALincludes the external capacitors,

the board parasitics, and the AD6600 parasitics. The parasitics

of the AD6600 (lead, internal bond pad and internal connec-

tions) at FLT and FLT are 1.75 pF 0.35 pF (differential).

FLT

FROM

GAIN STAGE

If the resistors are at maximum value (315 + 20%), the maxi-

mum allowable capacitance is C_TOTAL= 11.3 pF. If the duty

cycle is less than 50%, the maximum allowable capacitance is

further decreased to allow for settling.

CLAMP

ENCODE

Power Supplies

GND

Care should be taken when selecting a power source. Linear

supplies are strongly recommended. Switching supplies tend to

have radiated components that may be “received” by the AD6600.

Each of the power supply pins should be decoupled as closely to

the package as possible using 0.1 µF chip capacitors.

Figure 23. 4×/8× Amplifier Clamp Circuitry

Figure 24 shows why settling is important for this circuit. If the

4×/8× amp does not settle (come out of clamp), the amplitude

presented to the ADC will be decreased. This results in decreased

gain when the filter capacitance is too high.

The AD6600 has separate digital and analog power supply pins.

The analog supplies are denoted AVCC and the digital supply

pins are denoted DVCC. Although analog and digital supplies

may be tied together, best performance is achieved when the

supplies are separate. This is because the fast digital output

swings can couple switching current back into the analog sup-

plies. Note that AVCC must be held within 5% of 5 Volts; how-

ever, the DVCC supply may be varied according to output

digital logic family. The AD6600 is specified for DVCC = 3.3 V

as this is a common supply for digital ASICS.

ENCODE

HOLD

TRACK

HOLD

CLAMPED

RESONANT

FILTER

SETTLING

Figure 24. 4×/8× Amplifier Settling

This explains why the total capacitance allowed for the external

filter varies depending on the clock rate (actually encode clock

high time). If the encode is 13 MSPS and the duty cycle is 50%,

the allowable settling time is 38.5 ns (1/2 of the encode time).

Our assumption is that the amp should be allowed to settle to

1/4 LSB in this time period. This has been proven with both

simulation and empirical analysis. If the settling is assumed to

be an RC circuit, then:

Output Loading

Care must be taken when designing the data receivers for the

AD6600. Note from the equivalent circuits shown earlier (see

Equivalent Circuits) that D[10:0] and RSSI[2:0] contain a

500 Ω output series resistor. To minimize capacitive loading,

there should only be one gate on each output pin. Extra capaci-

tive loading will increase output timing and invalidate timing

specifications. CLK2× and AB_OUT do not contain the output

series resistors. Testing for digital output timing is performed

with 10 pF loads.

T = RC; t = time; n = number of bits

V_O= A 1− e^{t /T}

(

)

A − A / 2ⁿ= A 1− e^{t /T}

(

)

Layout Information

The schematic of the evaluation board (Figure 25) represents a

typical implementation of the AD6600. A multilayer board is

recommended to achieve best results. It is highly recommended

that high quality, ceramic chip capacitors be used to decouple

each supply pin to ground directly at the device. The pinout of

the AD6600 facilitates ease of use in the implementation of high

frequency, high resolution design practices. All of the digital

outputs are segregated to two sides of the chip, with the inputs

on the opposite side for isolation purposes.

2ⁿ

1−

= 1− e^{t /T}

2ⁿ

= e^{t /T}

 1 

= l n







ⁿ

T =

l n 2ⁿ

(

)

Care should be taken when routing the digital output traces. To

prevent coupling through the digital outputs into the analog

portion of the AD6600, minimal capacitive loading should be

placed on these outputs. It is recommended that a fanout of

only one be used for all AD6600 digital outputs.

× 0.5

(

)

38.5ns

ENCODE

C_TOTAL

= 13.6 pF

R × l n 8192

315Ω × l n 8192

(

)

(

)

The layout of the analog inputs and the external resonant filter

are critical. No digital traces must be routed near, under, or

above these portions of the circuit. The transformers used for

coupling into the analog inputs must be located as close as

possible to the analog inputs of the AD6600. The external reso-

nant filter components must be physically close to the filter-

input pins, yet separated from the analog inputs.

In this case, C_TOTALincludes all parasitics and external capaci-

tance. R is nominally 315 Ω. The 8192 is (4 × 2048), which is

1/4 LSB of the converter (11 bits, 2048).

REV. 0

–19–

1...17 18 192021 22 23...25

中文翻译

下载PDF

与AD6600AST相关器件

型号	品牌	获取价格	描述	数据表
AD6600AST-REEL	ADI	获取价格	IC 2-CH 11-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44, PLASTIC, LQFP-44, Analog t
AD6600ASTZ	ROCHESTER	获取价格	2-CH 11-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44, PLASTIC, LQFP-44
AD6600ASTZ-REEL	ADI	获取价格	Diversity Receiver Chipset
AD6600PCB	ADI	获取价格	Dual Channel, Gain-Ranging ADC with RSSI
AD-6600S	BOTHHAND	获取价格	ADSL TRANSFORMER
AD6600ST	ADI	获取价格	Dual Channel, Gain-Ranging ADC with RSSI
AD6600ST/PCB	ADI	获取价格	Dual Channel, Gain-Ranging ADC with RSSI
AD660AN	ADI	获取价格	Monolithic 16-Bit Serial/Byte DACPORT
AD660ANZ	ADI	获取价格	Monolithic 16-Bit Serial/Byte DACPORT
AD660ANZ1	ADI	获取价格	Monolithic 16-Bit Serial/Byte DACPORT

与AD6600AST相关文章

晶闸管阳极与阴极之间加电压时控制极的电流流动分析
2024-06-05

10
探究MOS管沟道夹断后载流子传输机制及其电路设计影响
2024-06-05

9
光敏电阻的工作原理、作用及检测方法
2024-06-05

8
ENC28J60以太网控制器全面解析：特性、应用、引脚说明
2024-06-05

6

产品中心

服务支持

精选活动

关于我们

帮助中心

AD6600AST

AD6600AST 技术参数

AD6600AST 数据手册

与AD6600AST相关器件

与AD6600AST相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD6600AST

AD6600AST 技术参数

AD6600AST 数据手册

与AD6600AST相关器件

与AD6600AST相关文章

您还可以找

您在本页遇到什么问题？