Datasheet > AD6438-2

AD6438-2

更新时间： 2024-02-13 14:53:26

品牌	Logo	应用领域
亚德诺 - ADI		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
28页	185K
描述
IC ATM NETWORK INTERFACE, PQFP144, LQFP-144, ATM/SONET/SDH IC

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技术参数
数据手册

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AD6438-2 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	144
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	S-PQFP-G144
长度：	20 mm	功能数量：	1
端子数量：	144	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.6 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH NETWORK INTERFACE
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	20 mm	Base Number Matches：	1

AD6438-2 数据手册

AD6438-2

Since this RAM is used by both the Tx and Rx paths, there exists

the possibility of memory contention if both want access to RAM

at the same time. The interface logic is designed to access the

RAM in two cycles, and as long as the RAM can support access

at this speed, there will be no contention.

BERT Testing

Serial Mode is designed to be used for BERT testing. In addi-

tion to the typical setting up of a TTC Fireberd 6000 tester, it is

sometimes necessary to invert the polarity on the transmit clock.

This is due to the fact that the Fireberd outputs data and clock

on the transmit side and the IC has its own output clock that is

used to sample the data.

The external interleaver RAM is operated in WE-controlled

mode (chip select held low by hardware) and needs access time

of <20 ns to operate without additional wait states.

If it is desired to automate the testing process with no manual

intervention, external hardware can be added to perform this

clock polarity adjustment function or the automated software

can be written to include the ability to invert the transmit clock

polarity via the control interface.

Interface Timing

All signals transmitted by the AD6439-2 to the AD6438-2 are

transmitted on the rising edge and sampled on the falling edge,

except for the Tx_DREQ signal, which is transmitted by the

AD6439-2 on the falling edge and sampled by the AD6438-2 on

the rising edge. All output signals from the AD6438-2 to the

AD6439-2 are transmitted by the AD6438-2 in the rising edge

and received by the AD6439-2 on the rising edge (see Table VIII,

Figure 23, Table XIV, Figure 24).

Enabling Serial Mode

To enable Serial Mode, it is necessary to set Bit 23 of OPTN 2

CMV to a 1.

Interleave RAM Interface

The AD6438-2 interfaces an external 32K × 8 interleave

RAM. The RAM interface consists of M_A[14:0], M_D[7:0],

NM_WE, and NM_OE.

CO/RT XMT AD6438-2 RECEIVE

TxC

MSB

LSB

TxD

TxB

CO/RT RECEIVE

AD6438-2 XMT

RxC

LSB

RxD

RxB

MSB

Figure 22. Serial Mode Timing

REV. 0

–23–

1...20 21 222324 25 26...28

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