Datasheet > AD6438-2

AD6438-2

更新时间： 2024-01-06 23:08:37

品牌	Logo	应用领域
亚德诺 - ADI		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
28页	185K
描述
IC ATM NETWORK INTERFACE, PQFP144, LQFP-144, ATM/SONET/SDH IC

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AD6438-2 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	144
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	S-PQFP-G144
长度：	20 mm	功能数量：	1
端子数量：	144	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.6 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH NETWORK INTERFACE
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	20 mm	Base Number Matches：	1

AD6438-2 数据手册

AD6438-2

Timing Details at 33 MHz

AD6435/AD6438-2 Differences

Timing specifications for the receiver side of a signal are the

measurement base for the AD6438-2’s ac characteristics. Setup

and hold times are measured as shown in Figure 20. Three-

state timing for the multi-PHY application (multiple PHY

devices, multiplexed multiple output signals) is defined as

shown in Figure 21. The timing references (t_T5to t_Tl2) are cov-

ered in Table XI and Table XII.

The AD6435 provides an STM interface that is compliant with

the original T1E1.4 standard. This part accepts a clock on the

transmit side and performs byte stuffing and robbing to allow

the modem to adapt to the incoming clock frequency. This is now

known as Framing Mode 0 in the more recent ANSI T1E1.4

Issue 2 and ITU 992.1 specifications. This part does not have

the capability to do Framing Modes 1, 2, and 3.

NOTE

The AD6438-2 provides a serial mode interface that differs

from STM Mode on the AD6435, in that the AD6438-2 has a

DPLL on the transmit side that provides a clock that is locked to

the ADSL line rate. The AD6438-2 can receive all Framing

Modes 0, 1, 2, and 3. The AD6438-2 transmits in Framing

Modes 1, 2, and 3. Framing Modes 0 and 1 have the same frame

structure. The only difference between the two modes is that

Framing Mode 1 never performs the synchronization action

using byte stuffing and robbing.

A → P defines a signal from the ATM layer to the PHY layer.

A ← P defines a signal from the PHY layer to the ATM layer.

SERIAL MODE

Serial Mode Description

Serial Mode provides a synchronous clock and serial data that pro-

vides access to the ADSL PMD layer of the AD6438-2. The Tx

and Rx clocks are locked to the ADSL payload data rate and are

output from the AD6438-2. The phase locking of the DPLL

(Digital Phase Lock Loop) provides the user access to Framing

Modes 1, 2, and 3.

The AD6438-2 Serial Mode was designed to provide a user

access to the PMD sublayer and enable modem to provide its

own external ATM TC layer. It was not intended to be used in

a modem compliant to the STM specification.

The Serial Mode bypasses all of the ATM TC sublayer incorpo-

rated into the AD6438-2. The serial interface on the AD6438-2

provides a bytes strobe that allows the user to align the ATM

bytes with the ADSL PMD sublayer bytes per the ITU G.992.1

specification.

To be a compliant STM modem, it would be necessary to pro-

vide a dual latency downstream path as well as Framing Mode 0

on the transmit side.

Advantage

The Serial Mode allows for the use of external asynchronous

devices to connect to the ADSL PMD sublayer, such as an

external ATM TC sublayer. The Serial Mode also allows for the

use of bit-error-rate testers.

t_T5, t

t_T6, t

INPUT SETUP TO CLOCK

INPUT HOLD FROM CLOCK

Figure 20. Setup and Hold Time Definition (Single and Multi-PHY)

CLOCK

SIGNAL GOING

LOW IMPEDANCE

TO CLOCK

SIGNAL GOING

HIGH IMPEDANCE

TO CLOCK

t_T9

t_T10

t_T12

t_T11

SIGNAL GOING

LOW IMPEDANCE

FROM CLOCK

SIGNAL GOING

HIGH IMPEDANCE

FROM CLOCK

Figure 21. Three-State Timing (Multi-PHY, Multiple Devices Only)

REV. 0

–22–

1...19 20 212223 24 25...28

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