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AD5621AKSZ PDF预览

AD5621AKSZ

更新时间: 2024-01-01 07:53:50
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 466K
描述
2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit nanoDAC, SPI Interface in LFCSP and SC70

AD5621AKSZ 技术参数

生命周期:Obsolete包装说明:TSSOP, TSSOP6,.08
Reach Compliance Code:compliant风险等级:5.84
转换器类型:D/A CONVERTER输入位码:BINARY
JESD-30 代码:R-PDSO-G6最大线性误差 (EL):0.02%
位数:12功能数量:1
端子数量:6最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP6,.08
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3/5 V认证状态:Not Qualified
最大稳定时间:18 µs子类别:Other Converters
最大压摆率:0.1 mA表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUALBase Number Matches:1

AD5621AKSZ 数据手册

 浏览型号AD5621AKSZ的Datasheet PDF文件第3页浏览型号AD5621AKSZ的Datasheet PDF文件第4页浏览型号AD5621AKSZ的Datasheet PDF文件第5页浏览型号AD5621AKSZ的Datasheet PDF文件第7页浏览型号AD5621AKSZ的Datasheet PDF文件第8页浏览型号AD5621AKSZ的Datasheet PDF文件第9页 
AD5601/AD5611/AD5621  
Data Sheet  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
AD5601/  
AD5611/  
V
1
2
6
5
4
V
OUT  
DD  
V
1
2
3
6
5
4
SYNC  
SCLK  
SDIN  
OUT  
AD5601/  
AD5611/  
AD5621  
TOP VIEW  
(Not to Scale)  
SCLK  
SDIN  
GND  
AD5621  
GND  
TOP VIEW  
(Not to Scale)  
SYNC  
3
V
DD  
NOTES:  
1. CONNECT THE EXPOSED PAD TO GND.  
Figure 3. 6-Lead SC70 Pin Configuration  
Figure 4. 6-Lead LFCSP Pin Configuration  
Table 5. Pin Function Descriptions  
SC70 LFCSP  
Pin No. Pin No.  
Mnemonic  
Description  
1
4
SYNC  
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input  
data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling  
edges of the clocks that follow. The DAC is updated following the 16th clock cycle, unless SYNC is  
taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write  
sequence is ignored by the DAC.  
2
3
4
2
3
1
SCLK  
SDIN  
VDD  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock  
input. Data can be transferred at rates up to 30 MHz.  
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling  
edge of the serial clock input.  
Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2.7 V to 5.5 V. VDD should be  
decoupled to GND.  
5
6
5
6
GND  
VOUT  
EP  
Ground. Ground reference point for all circuitry on the AD5601/AD5611/AD5621.  
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.  
Exposed Pad. Connect to GND.  
Rev. G | Page 6 of 24  
 
 
 

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