Datasheet > AD5592R

AD5592R

更新时间： 2022-02-26 11:19:09

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
42页	1002K
描述
Control and monitoring

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中文翻译

获取价格

数据手册

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AD5592R 数据手册

AD5592R

Data Sheet

Table 4. AD5592R-1 Timing Characteristics

Parameter

1.8 V ≤ V_LOGIC< 3 V

3 V ≤ V_LOGIC≤ 5.5 V

Unit

Test Conditions/Comments

SCLK cycle time, write operation

SCLK cycle time, read operation

SCLK high time

t₁

ns min

µs max

ns min

ns max

t₂

t₃

t₄

SCLK low time

SYNC to SCLK falling edge setup time

Data setup time

Data hold time

SCLK falling edge to SYNC rising edge

t₅

t₆

t₇

t₈

Minimum SYNC high time for write operations

Minimum SYNC high time for register read operations

SYNC rising edge to next SCLK falling edge

SCLK rising edge to SDO valid

t₉

t₁₀

200µA

TO OUTPUT

1.6V

25pF

200µA

Figure 3. Load Circuit for Logic Output (SDO) Timing Specifications

t₁

t₉

SCLK

t₂

t₃

t₇

t₄

t₈

SYNC

t₆

t₅

SDI

DB15

DB0

t₁₀

SDO

DB0

Figure 4. Timing Diagram

Rev. C | Page 8 of 42

1...5 6 789 10 11...42

中文翻译

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