Datasheet > AD5592R

AD5592R

更新时间： 2022-02-26 11:19:09

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
42页	1002K
描述
Control and monitoring

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AD5592R 数据手册

Data Sheet

AD5592R

Parameter

Min

Typ

Max

Unit¹

Test Conditions/Comments

V_DD= 3 V (Normal Mode)

1.1

I/O0 to I/O7 are DACs, internal reference,

gain = 1

I/O0 to I/O7 are DACs, external reference,

gain = 1

I/O0 to I/O7 are DACs and sampled by the

ADC, internal reference, gain = 1

I/O0 to I/O7 are DACs and sampled by the

ADC, external reference, gain = 1

I/O0 to I/O7 are ADCs, internal reference,

gain = 1

1.1

0.78

0.75

0.5

I/O0 to I/O7 are ADCs, external reference,

gain = 1

0.45

I/O0 to I/O7 are general-purpose outputs

I/O0 to I/O7 are general-purpose inputs

AD5592R-1 only

V_LOGIC

I_LOGIC

1.8

V_DD

µA

AD5592R-1 only

¹All specifications expressed in decibels are referred to full-scale input (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise noted.

²Guaranteed by design and characterization; not production tested.

³DC specifications tested with the outputs unloaded, unless otherwise noted. Linearity calculated using a code range of 8 to 4095. There is an upper dead band of

10 mV when V_REF= V_DD

⁴When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output

devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 33).

TIMING CHARACTERISTICS

Guaranteed by design and characterization, not production tested; all input signals are specified with t_R= t_F= 5 ns (10% to 90% of V_DD

and timed from a voltage level of (V_IL+ V_IH)/2; T_A= T_MINto T_MAX, unless otherwise noted.

)

Table 3. AD5592R Timing Characteristics

Parameter

2.7 V ≤ V_DD< 3 V

3 V ≤ V_DD≤ 5.5 V

Unit

Test Conditions/Comments

t₁

ns min

µs max

ns min

ns max

ns min

SCLK cycle time, write operation

SCLK cycle time, read operation

SCLK high time

t₂

t₃

t₄

SCLK low time

SYNC falling edge to SCLK falling edge setup time

SYNC falling edge to SCLK falling edge setup time¹

Data setup time

t₅

t₆

t₇

t₈

Data hold time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time for register write operations

Minimum SYNC high time for register read operations

SYNC rising edge to next SCLK falling edge

SCLK rising edge to SDO valid

t₉

t₁₀

t₁₁

250

RESET low pulse width (not shown in Figure 4)

¹When reading an ADC conversion.

Rev. C | Page 7 of 42

1...4 5 678 9 10...42

下载PDF

与AD5592R相关器件

型号	品牌	描述	获取价格	数据表
AD5592RBCBZ-1-RL7	ADI	暂无描述	获取价格
AD5592RBCBZ-RL7	ADI	8 Channel, 12-Bit, Configurable ADC/DAC with on-chip Reference, SPI interface	获取价格
AD5592RBCPZ-1-RL7	ADI	Control and monitoring	获取价格
AD5592RBCPZ-RL7	ADI	8 Channel, 12-Bit, Configurable ADC/DAC with on-chip Reference, SPI interface	获取价格
AD5592RBRUZ	ADI	Control and monitoring	获取价格
AD5592RBRUZ-RL7	ADI	Control and monitoring	获取价格