AD5532HS

更新时间： 2024-02-04 19:02:58

品牌	Logo	应用领域
亚德诺 - ADI		转换器数模转换器
页数	文件大小	规格书
12页	180K
描述
32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interface

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技术参数
数据手册

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AD5532HS 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	LBGA,	针数：	74
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.64
最大模拟输出电压：	2.5 V	最小模拟输出电压：	-2.5 V
转换器类型：	D/A CONVERTER	输入位码：	BINARY
输入格式：	SERIAL	JESD-30 代码：	S-PBGA-B74
JESD-609代码：	e1	长度：	12 mm
最大线性误差 (EL)：	0.39%	湿度敏感等级：	3
位数：	14	功能数量：	1
端子数量：	74	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1.7 mm
标称安定时间 (tstl)：	10 µs	标称供电电压：	5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40	宽度：	12 mm
Base Number Matches：	1

AD5532HS 数据手册

AD5532HS

MICROPROCESSOR INTERFACING

AD5532HS-to-ADSP-21xx Interface

The ADSP-21xx family of DSPs are easily interfaced to the

AD5532HS without the need for extra logic.

AD5532HS-to-PIC16C6x/7x Interface

The PIC16C6x/7x Synchronous Serial Port (SSP) is configured

as an SPI Master with the Clock Polarity bit = 0. This is done

by writing to the Synchronous Serial Port Control Register

(SSPCON). See user PIC16/17 Microcontroller User Manual.

In this example I/O port RA1 is being used to pulse SYNC

and enable the serial port of the AD5532HS. This microcontroller

transfers only eight bits of data during each serial transfer

operation; therefore, three consecutive write operations are

necessary to transmit 19 bits of data. Data is transmitted MSB

first. It is important to left-justify the data in the SPDR register

so that the first 19 bits transmitted contain valid data. RA1

must be pulled low to start a transfer. It is taken high and pulled

low again before any further write cycles can take place. Figure 5

shows the connection diagram.

A data transfer is initiated by writing a word to the Tx register

after the SPORT has been enabled. In a write sequence, data is

clocked out on each rising edge of the DSP’s serial clock and

clocked into the AD5532HS on the falling edge of its SCLK.

The easiest way to provide the 19-bit data-word required by

the AD5532HS, is to transmit two 10-bit data-words from the

ADSP-21xx. Ensure that the data is positioned correctly in the

TX register so that the first 19 bits transmitted contain valid

data. The SPORT control register should be set up as follows:

TFSW = 1, Alternate Framing

INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

ISCLK = 1, Internal Serial Clock

PIC16C6x/7x*

AD5532HS*

SCLK

SCK/RC3

TFSR

ITFS

= 1, Frame Every Word

= 1, Internal Framing Signal

SDI/RC4

RA1

SYNC

SLEN = 1001, 10-Bit Data Word

Figure 3 shows the connection diagram.

*ADDITIONAL PINS OMITTED FOR CLARITY

ADSP-2101/

ADSP-2103*

AD5532HS*

Figure 5. AD5532HS-to-PIC16C6x/7x Interface

SCLK

AD5532HS-to-8051 Interface

The AD5532HS requires a clock synchronized to the serial

data. The 8051 serial interface must therefore be operated in

Mode 0. In this mode serial data exits the 8051 through RxD

and a shift clock is output on TxD. The SYNC signal is derived

from a port line (P1.1). Figure 6 shows how the 8051 is connected

to the AD5532HS. Because the AD5532HS shifts data out on

the rising edge of the shift clock and latches data in on the

falling edge, the shift clock must be inverted. Note also that

the AD5532HS requires its data with the MSB first. Since the

8051 outputs the LSB first, the transmit routine must take this

into account.

TFS

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 3. AD5532HS-to-ADSP-2101/ADSP-2103 Interface

AD5532HS-to-MC68HC11 Interface

The Serial Peripheral Interface (SPI) on the MC68HC11 is

configured for Master Mode (MSTR = 1), Clock Polarity Bit

(CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is

configured by writing to the SPI Control Register (SPCR)—see

68HC11 User Manual. SCK of the 68HC11 drives the SCLK of

the AD5532HS and the MOSI output drives the serial data line

(D_IN) of the AD5532HS. The SYNC signal is derived from a port

line (PC7). When data is being transmitted to the AD5532HS, the

SYNC line is taken low (PC7). Data appearing on the MOSI

output is valid on the falling edge of SCK. The 68HC11 transfers

only eight bits of data during each serial transfer operation;

therefore, three consecutive write operations are necessary to

transmit 19 bits of data. Data is transmitted MSB first. It is

important to left-justify the data in the SPDR register so that

the first 19 bits transmitted contain valid data. PC7 must be

pulled low to start a transfer. It is taken high and pulled low

again before any further write cycles can take place. See Figure 4.

8051*

AD5532HS*

SCLK

TxD

RxD

P1.1

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 6. AD5532HS-to-8051 Interface

MC68HC11*

AD5532HS*

SCLK

SCK

MOSI

PC7

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 4. AD5532HS-to-MC68HC11 Interface

REV. 0

–9–

1...6 7 8910 11 12

中文翻译

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