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AD5392BCP-5-REEL

更新时间： 2024-11-08 22:27:03
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器
页数 文件大小 规格书
44页 1446K
描述
8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs

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AD5392BCP-5-REEL 数据手册

 浏览型号AD5392BCP-5-REEL的Datasheet PDF文件第2页浏览型号AD5392BCP-5-REEL的Datasheet PDF文件第3页浏览型号AD5392BCP-5-REEL的Datasheet PDF文件第4页浏览型号AD5392BCP-5-REEL的Datasheet PDF文件第5页浏览型号AD5392BCP-5-REEL的Datasheet PDF文件第6页浏览型号AD5392BCP-5-REEL的Datasheet PDF文件第7页 
8-/16-Channel, 3 V/5 V, Serial Input, Single-  
Supply, 12-/14-Bit Voltage Output DACs  
AD5390/AD5391/AD5392  
FEATURES  
INTEGRATED FUNCTIONS  
AD5390: 16-channel, 14-bit voltage output DAC  
AD5391: 16-channel, 12-bit voltage output DAC  
AD5392: 8-channel, 14-bit voltage output DAC  
Guaranteed monotonic  
Channel monitor  
Simultaneous output update via LDAC  
Clear function to user-programmable code  
Amplifier boost mode to optimize slew rate  
User-programmable offset and gain adjust  
Toggle mode enables square wave generation  
Thermal monitor  
INL: 1 LSB max (AD5391)  
3 LSB max (AD5390-5/AD5392-5)  
4 LSB max (AD5390-3/AD5392-3)  
On-chip 1.25 V/2.5 V, 10 ppm/°C reference  
Temperature range: −40°C to +85°C  
Rail-to-rail output amplifier  
Power-down mode  
APPLICATIONS  
Instrumentation and industrial control  
Power amplifier control  
Level setting (ATE)  
Package types:  
Control systems  
64-lead LFCSP (9 mm × 9 mm)  
52-lead LQFP (10 mm × 10 mm)  
User interfaces:  
Microelectromechanical systems (MEMs)  
Variable optical attenuators (VOAs)  
Optical transceivers (MSA 300, XFP)  
Serial SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible  
(featuring data readback)  
I2C®-compatible interface  
FUNCTIONAL BLOCK DIAGRAM  
DV  
DD  
(×  
2)  
DGND (  
×
2)  
AV  
DD  
(
×2)  
AGND (  
×
2)  
DAC_GND (  
×2)  
REF_GND  
REFOUT/REFIN SIGNAL_GND (  
×2)  
1.25V/2.5V  
REFERENCE  
AD5390  
2
SPI/I C  
INPUT  
REG  
0
DAC  
REG  
0
14  
14  
14  
14  
14  
14  
DAC 0  
DCEN/AD1  
VOUT 0  
14  
14  
m REG0  
c REG0  
DIN/SDA  
SCLK/SCL  
SYNC/AD0  
SDO  
R
R
STATE  
R
R
INTERFACE MACHINE  
CONTROL  
LOGIC  
AND  
CONTROL  
LOGIC  
INPUT  
REG  
1
DAC  
REG  
1
14  
14  
DAC 1  
VOUT 1  
VOUT 2  
VOUT 3  
VOUT 4  
VOUT 5  
VOUT 6  
14  
14  
m REG1  
c REG1  
BUSY  
PD  
INPUT  
REG  
6
DAC  
REG  
6
14  
14  
14  
14  
14  
14  
14  
14  
DAC 6  
CLR  
POWER-ON  
RESET  
14  
14  
RESET  
m REG6  
c REG6  
R
R
R
R
V
0
V 15  
IN  
IN  
INPUT  
DAC  
REG  
7
REG  
7
DAC 7  
VOUT 7  
VOUT 8  
14  
14  
MON_IN1  
MON_IN2  
m REG7  
c REG7  
MUX  
×
2
VOUT 15  
LDAC  
MON_OUT  
Figure 1.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  
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