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AD5336

更新时间： 2024-02-17 21:25:53
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 352K
描述
2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

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AD5336 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP-28针数：24
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.44
最大模拟输出电压：2.999 V最小模拟输出电压：0.001 V
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：PARALLEL, 8 BITSJESD-30 代码：R-PDSO-G24
JESD-609代码：e3长度：9.7 mm
最大线性误差 (EL)：0.3906%湿度敏感等级：1
位数：10功能数量：4
端子数量：24最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP28,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：2.5/5.5 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大稳定时间：9 µs标称安定时间 (tstl)：7 µs
子类别：Other Converters最大压摆率：0.9 mA
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：4.4 mm

AD5336 数据手册

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AD5330/AD5331/AD5340/AD5341  
The low data byte of the AD5341 consists of data bits 0 to 7 at  
data inputs DB0 to DB7, while the high byte consists of data  
bits 8 to 11 at data inputs DB0 to DB3 as shown in Figure 29.  
DB4 to DB7 are ignored during a high-byte write, but they may  
be used for data to set up the reference input as buffered/  
unbuffered, and buffer amplifier gain. See Figure 33.  
reduced when the DAC is not in use by putting it into power-  
down mode, which is selected by taking pin PD low.  
When the PD pin is high, the DAC works normally with a  
typical power consumption of 140 µA at 5 V (115 µA at 3 V).  
In power-down mode, however, the supply current falls to  
200 nA at 5 V (80 nA at 3 V) when the DAC is powered-down.  
Not only does the supply current drop, but the output stage is  
also internally switched from the output of the amplifier mak-  
ing it open-circuit. This has the advantage that the output is  
three-state while the part is in power-down mode and pro-  
vides a defined input condition for whatever is connected to  
the output of the DAC amplifier. The output stage is illus-  
trated in Figure 30.  
HIGH BYTE  
X
X
X
X
DB11 DB10 DB9 DB8  
LOW BYTE  
DB5 DB4  
DB2  
DB1 DB0  
DB7 DB6  
X = UNUSED BIT  
DB3  
Figure 29. Data Format for AD5341  
POWER-ON RESET  
The AD5330/AD5331/AD5340/AD5341 are provided with a  
power-on reset function, so that they power up in a defined state.  
The power-on state is:  
RESISTOR  
STRING DAC  
AMPLIFIER  
V
OUT  
POWER-DOWN  
CIRCUITRY  
• Normal Operation  
• Reference Input Unbuffered  
• 0 – VREF Output Range  
• Output Voltage Set to 0 V  
Figure 30. Output Stage During Power-Down  
The bias generator, the output amplifier, the resistor string,  
and all other associated linear circuitry are shut down when  
the power-down mode is activated. However, the contents  
of the registers are unaffected when in power-down. The time  
to exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs  
when VDD = 3 V. This is the time from a rising edge on the  
PD pin to when the output voltage deviates from its power-  
down voltage. See Figure 22.  
Both input and DAC registers are filled with zeros and remain so  
until a valid write sequence is made to the device. This is  
particularly useful in applications where it is important to know  
the state of the DAC outputs while the device is powering up.  
POWER-DOWN MODE  
The AD5330/AD5331/AD5340/AD5341 have low power con-  
sumption, dissipating only 0.35 mW with a 3 V supply and  
0.7 mW with a 5 V supply. Power consumption can be further  
Table I. AD5330/AD5331/AD5340 Truth Table  
CLR  
LDAC  
CS  
WR  
Function  
1
1
0
1
1
1
1
1
X
1
0
0
1
X
1
X
0➝1  
0➝1  
X
No Data Transfer  
No Data Transfer  
Clear All Registers  
Load Input Register  
Load Input Register and DAC Register  
Update DAC Register  
X
X
0
0
X
X = don’t care.  
Table II. AD5341 Truth Table  
CLR  
LDAC  
CS  
WR  
HBEN  
Function  
1
1
0
1
1
1
1
1
1
1
X
1
1
0
0
0
1
X
1
X
0➝1  
0➝1  
0➝1  
0➝1  
X
X
X
X
0
1
0
No Data Transfer  
No Data Transfer  
Clear All Registers  
Load Low-Byte Input Register  
Load High-Byte Input Register  
Load Low-Byte Input Register and DAC Register  
Load High-Byte Input Register and DAC Register  
Update DAC Register  
X
X
0
0
0
0
X
1
X
X = don’t care.  
–15–  
REV. 0  
1...12131415161718...20

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