AD5313RBRUZ-RL7

更新时间： 2024-02-15 05:12:17

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
28页	698K
描述
Dual, 10-Bit nanoDAC with 2 ppm/C Reference, SPI Interface

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数据手册
替代型号

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AD5313RBRUZ-RL7 数据手册

AD5313R

Data Sheet

LDAC

Deferred DAC Updating (

Pulsed Low)

is held high while data is clocked into the input register

using Command 0001. Both DAC outputs are asynchronously

LDAC SYNC

LOAD DAC (HARDWARE LDAC PIN)

LDAC

The AD5313R DACs have double buffered interfaces consisting

of two banks of registers: input registers and DAC registers. The

user can write to any combination of the input registers. Updates

updated by taking

low after

is taken high. The

LDAC

to the DAC register are controlled by the

pin.

LDAC

update then occurs on the falling edge of

OUTPUT

AMPLIFIER

LDAC MASK REGISTER

LDAC

Command 0101 is reserved for a software

mask function,

10-BIT

DAC

REF

OUT

which allows the address bits to be ignored. A write to the DAC

LDAC

using Command 0101 loads the 4-bit

to DB0). The default setting for each channel is 0; that is,

LDAC

mask register (DB3

DAC

LDAC

the

the DAC channel to ignore transitions on the

LDAC

pin works normally. Setting the selected bit to 1 forces

LDAC

pin, regardless

pin. This flexibility is useful

in applications where the user wishes to select which channels

LDAC

of the state of the hardware

INPUT

respond to the

pin.

mask register gives the user extra flexibility and control

LDAC LDAC

LDAC

The

over the hardware

(DB3, DB0) to 0 for a DAC channel means that the update of

LDAC

SCLK

SYNC

SDIN

INTERFACE

LOGIC

SDO

pin (see Table 13). Setting an

bit

this channel is controlled by the hardware

LDAC

pin.

Figure 44. Simplified Diagram of Input Loading Circuitry for a Single DAC

LDAC

Instantaneous DAC Updating (

Held Low)

Table 13.

Load LDAC Register

Bits

Overwrite Definition

LDAC

is held low while data is clocked into the input register

using Command 0001. Both the addressed input register and

SYNC

LDAC

(DB3, DB0)

Operation

LDAC

the DAC register are updated on the rising edge of

, and

LDAC

1 or 0

X¹

then the output begins to change (see Table 14 and Table 15).

Determined by the LDAC pin.

DAC channels update and override

the LDAC pin. DAC channels see

the LDAC pin as set to 1.

¹X = don’t care.

LDAC

Table 14. 24-Bit Input Shift Register Contents for

Operation

DB23

DB0

(LSB)

(MSB) DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB4

DB3

DB2

DB1

DAC B

DAC A

Command bits (C3 to C0)

Address bits, don’t care

Don’t care

Setting the LDAC bit to 1 overrides the LDAC pin

¹X = don’t care.

LDAC

Table 15. Write Commands and

Pin Truth Table

Hardware

Pin State

V_LOGIC

LDAC

Command

Description

Input Register Contents

Data update

DAC Register Contents

No change (no update)

Data update

0001

Write to Input Register n

(dependent on LDAC)

GND²

Data update

0010

0011

Update DAC Register n with

contents of Input Register n

V_LOGIC

GND

No change

Updated with input register contents

Data update

No change

Write to and update DAC Channel n

V_LOGIC

GND

Data update

LDAC

A high-to-low hardware

pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked

mask register.

pin is permanently tied low, the

LDAC

(blocked) by the

LDAC

mask bits are ignored.

When the

Rev. 0 | Page 22 of 28

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AD5313RBRUZ-RL7 替代型号

型号	品牌	替代类型	描述	数据表
AD5313RBRUZ	ADI	完全替代	Dual, 10-Bit nanoDAC with 2 ppm/C Reference, SPI Interface

与AD5313RBRUZ-RL7相关器件

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AD5314ACPZ-REEL7	ADI	获取价格	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output
AD5314ACPZ-WP	ADI	获取价格	IC SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, DSO10, LEAD FREE, 3 X 3 MM, LFCSP
AD5314ARM	ADI	获取价格	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output
AD5314ARM-REEL7	ADI	获取价格	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output
AD5314ARMZ	ADI	获取价格	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output
AD5314ARMZ-REEL7	ADI	获取价格	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output
AD5314BCPZ-REEL7	ADI	获取价格	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output
AD5314BCPZ-WP	ADI	获取价格	IC SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, DSO10, LEAD FREE, 3 X 3 MM, LFCSP

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