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AD5231BRUZ50 PDF预览

AD5231BRUZ50

更新时间： 2024-02-14 20:25:00
品牌 Logo 应用领域
亚德诺 - ADI 数字电位计存储
页数 文件大小 规格书
28页 536K
描述
Nonvolatile Memory, 1024-Position Digital Potentiometer

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AD5231BRUZ50 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.13
其他特性：LINEAR OR LOG TAPER SETTINGS; NONVOLATILE MEMORY; CAN ALSO OPERATE FROM +/-2.25V TO +/-2.75V SUPPLY标称带宽：0.085 kHz
控制接口：3-WIRE SERIAL转换器类型：DIGITAL POTENTIOMETER
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：5 mm湿度敏感等级：1
功能数量：1位置数：1024
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：+-2.5/3/5 V
认证状态：Not Qualified电阻定律：LOGARITHMIC
最大电阻容差：20%最大电阻器端电压：3 V
最小电阻器端电压：座面最大高度：1.2 mm
子类别：Digital Potentiometers标称供电电压：3 V
表面贴装：YES标称温度系数：600 ppm/ °C
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
标称总电阻：50000 Ω宽度：4.4 mm
Base Number Matches：1

AD5231BRUZ50 数据手册

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AD5231  
Data Sheet  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
O1  
CLK  
SDI  
O2  
RDY  
CS  
AD5231  
SDO  
GND  
PR  
TOP VIEW  
(Not to Scale)  
WP  
V
SS  
V
DD  
T
A
W
B
Figure 5. Pin Configuration  
Table 4. Pin Function Descriptions  
Pin No. Mnemonic Description  
1
O1  
Nonvolatile Digital Output 1. ADDR = 0x1, data bit position D0. For example, to store O1 high, the data bit  
format is 0x310001.  
2
3
4
CLK  
SDI  
SDO  
Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.  
Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.  
Serial Data Output Pin. Serves readback and daisy-chain functions.  
Command 9 and Command 10 activate the SDO output for the readback function, delayed by 24 or 25 clock  
pulses, depending on the clock polarity before and after the data-word (see Figure 3, Figure 4, and Table 7).  
In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses  
depending on the clock polarity (see Figure 3 and Figure 4). This previously shifted-out SDI can be used for  
daisy-chaining multiple devices.  
Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed.  
5
6
GND  
VSS  
Ground Pin. Logic ground reference.  
Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual-supply applications, it must be  
able to sink 40 mA for 25 ms when storing data to EEMEM.  
7
8
T
B
Reserved for factory testing. Connect to VDD or VSS.  
Terminal B of RDAC.  
9
W
A
VDD  
WP  
Wiper Terminal of RDAC. ADDR (RDAC) = 0x0.  
Terminal A of RDAC.  
Positive Power Supply Pin.  
Optional Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR and  
Instruction 1 and Instruction 8 and refreshes the RDAC register from EEMEM. Execute a NOP instruction before  
returning to WP high. Tie WP to VDD, if not used.  
10  
11  
12  
13  
PR  
Optional Hardware Override Preset Pin. Refreshes the scratchpad register with current contents of the EEMEM  
register. Factory default loads midscale 51210 until EEMEM is loaded with a new value by the user. PR is activated  
at the logic high transition. Tie PR to VDD, if not used.  
14  
15  
16  
CS  
Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.  
Ready. Active-high open-drain output. Identifies completion of Instructions 2, 3, 8, 9, 10, and PR.  
RDY  
O2  
Nonvolatile Digital Output 2. ADDR = 0x1, data bit position D1. For example, to store O2 high, the data bit  
format is 0x310002.  
Rev. D | Page 8 of 28  
 
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