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AD5231BRUZ50 PDF预览

AD5231BRUZ50

更新时间： 2024-01-23 00:13:42
品牌 Logo 应用领域
亚德诺 - ADI 数字电位计存储
页数 文件大小 规格书
28页 536K
描述
Nonvolatile Memory, 1024-Position Digital Potentiometer

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AD5231BRUZ50 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.13
其他特性：LINEAR OR LOG TAPER SETTINGS; NONVOLATILE MEMORY; CAN ALSO OPERATE FROM +/-2.25V TO +/-2.75V SUPPLY标称带宽：0.085 kHz
控制接口：3-WIRE SERIAL转换器类型：DIGITAL POTENTIOMETER
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：5 mm湿度敏感等级：1
功能数量：1位置数：1024
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：+-2.5/3/5 V
认证状态：Not Qualified电阻定律：LOGARITHMIC
最大电阻容差：20%最大电阻器端电压：3 V
最小电阻器端电压：座面最大高度：1.2 mm
子类别：Digital Potentiometers标称供电电压：3 V
表面贴装：YES标称温度系数：600 ppm/ °C
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
标称总电阻：50000 Ω宽度：4.4 mm
Base Number Matches：1

AD5231BRUZ50 数据手册

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Data Sheet  
AD5231  
TIMING CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS  
VDD = 3 V to 5.5 V, VSS = 0 V, and −40°C < TA < +85°C, unless otherwise noted.  
Table 2.  
Parameter  
INTERFACE TIMING CHARACTERISTICS2, 3  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
Clock Cycle Time (tCYC  
CS Setup Time  
)
t1  
t2  
20  
10  
1
ns  
ns  
tCYC  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCYC  
ns  
ms  
ms  
μs  
μs  
ns  
CLK Shutdown Time to CS Rise  
Input Clock Pulse Width  
Data Setup Time  
t3  
t4, t5  
t6  
t7  
Clock level high or low  
From positive CLK transition  
From positive CLK transition  
10  
5
5
Data Hold Time  
CS to SDO-SPI Line Acquire  
CS to SDO-SPI Line Release  
CLK to SDO Propagation Delay4  
CLK to SDO Data Hold Time  
CS High Pulse Width5  
t8  
40  
50  
50  
t9  
t10  
t11  
t12  
RP = 2.2 kΩ, CL < 20 pF  
RP = 2.2 kΩ, CL < 20 pF  
0
10  
4
CS High to CS High5  
t13  
RDY Rise to CS Fall  
t14  
0
CS Rise to RDY Fall Time  
Store/Read EEMEM Time6  
Power-On EEMEM Restore Time  
Dynamic EEMEM Restore Time  
WP High or Low to CS Fall Time  
t15  
0.1  
25  
140  
140  
40  
0.15  
t16  
Applies to instructions 0x2, 0x3, and 0x9  
RAB = 10 kΩ  
RAB = 10 kΩ  
tEEMEM1  
tEEMEM2  
tWP  
CS Rise to Clock Rise/Fall Setup  
t17  
10  
50  
ns  
ns  
μs  
Preset Pulse Width (Asynchronous)  
Preset Response Time to Wiper Setting  
tPRW  
tPRESP  
Not shown in timing diagram  
PR pulsed low to refresh wiper positions  
70  
FLASH/EE MEMORY RELIABILITY  
Endurance7  
Data Retention8  
100  
kCycles  
Years  
100  
1 Typical values represent average readings at 25°C and VDD = 5 V.  
2 Guaranteed by design and not subject to production test.  
3 See timing diagrams (Figure 3 and Figure 4) for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed  
from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 35 V.  
4 Propagation delay depends on the value of VDD, RPULL-UP, and CL.  
5 Valid for commands that do not activate the RDY pin.  
6
PR  
RDY pin low only for Instructions 2, 3, 8, 9, 10, and the hardware pulse: CMD_2, 3 ~ 20 ms; CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.12 ms. Device operation at TA = −40°C and  
VDD < 3 V extends the EEMEM store time to 35 ms.  
7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.  
8 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV  
derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section.  
Rev. D | Page 5 of 28  
 
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