Data Sheet
AD5231
TIMING CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 3 V to 5.5 V, VSS = 0 V, and −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
INTERFACE TIMING CHARACTERISTICS2, 3
Symbol
Conditions
Min
Typ1
Max
Unit
Clock Cycle Time (tCYC
CS Setup Time
)
t1
t2
20
10
1
ns
ns
tCYC
ns
ns
ns
ns
ns
ns
ns
ns
tCYC
ns
ms
ms
μs
μs
ns
CLK Shutdown Time to CS Rise
Input Clock Pulse Width
Data Setup Time
t3
t4, t5
t6
t7
Clock level high or low
From positive CLK transition
From positive CLK transition
10
5
5
Data Hold Time
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay4
CLK to SDO Data Hold Time
CS High Pulse Width5
t8
40
50
50
t9
t10
t11
t12
RP = 2.2 kΩ, CL < 20 pF
RP = 2.2 kΩ, CL < 20 pF
0
10
4
CS High to CS High5
t13
RDY Rise to CS Fall
t14
0
CS Rise to RDY Fall Time
Store/Read EEMEM Time6
Power-On EEMEM Restore Time
Dynamic EEMEM Restore Time
WP High or Low to CS Fall Time
t15
0.1
25
140
140
40
0.15
t16
Applies to instructions 0x2, 0x3, and 0x9
RAB = 10 kΩ
RAB = 10 kΩ
tEEMEM1
tEEMEM2
tWP
CS Rise to Clock Rise/Fall Setup
t17
10
50
ns
ns
μs
Preset Pulse Width (Asynchronous)
Preset Response Time to Wiper Setting
tPRW
tPRESP
Not shown in timing diagram
PR pulsed low to refresh wiper positions
70
FLASH/EE MEMORY RELIABILITY
Endurance7
Data Retention8
100
kCycles
Years
100
1 Typical values represent average readings at 25°C and VDD = 5 V.
2 Guaranteed by design and not subject to production test.
3 See timing diagrams (Figure 3 and Figure 4) for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed
from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 35 V.
4 Propagation delay depends on the value of VDD, RPULL-UP, and CL.
5 Valid for commands that do not activate the RDY pin.
6
PR
RDY pin low only for Instructions 2, 3, 8, 9, 10, and the hardware pulse: CMD_2, 3 ~ 20 ms; CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.12 ms. Device operation at TA = −40°C and
VDD < 3 V extends the EEMEM store time to 35 ms.
7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
8 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section.
Rev. D | Page 5 of 28