Low Cost, 14-Bit, Dual Channel
Synchro/Resolver-to-Digital Converter
Data Sheet
AD2S44
The core of each conversion is performed by state-of-the-art mono-
lithic, integrated circuits manufactured by the Analog Devices, Inc.,
proprietary BiMOS II process, which combines the advantages of
low power CMOS digital logic with bipolar linear circuits. The
use of these ICs keeps the internal component count low and
ensures high reliability.
FEATURES
Low per-channel cost
32-lead DIL hybrid package
2.6 arc minute accuracy
14-bit resolution
Built-in test
Independent reference inputs
High tracking rate
BIT
The built-in test (
) facility can be used in failsafe systems to
provide an indication of whether the converter is tracking
accurately.
APPLICATIONS
Gimbal/gyro control systems
Robotics
Engine controllers
Coordinate conversion
Military servo control systems
Fire control systems
Avionic systems
Each channel incorporates a high accuracy differential condi-
tioning circuit for signal inputs providing more than 74 dB of
common-mode rejection. Options are available for both synchro
and resolver format inputs. The converter output is via a three-state
transparent latch allowing data to be read without interruption
B
OE
of the converter operation. The A/ and
control lines select
the channel and present the digital position to the common
data outputs.
Antenna monitoring
CNC machine tooling
The AD2S44 also features independent reference inputs where
different reference frequencies can be used for each channel.
GENERAL DESCRIPTION
The AD2S44 is a 14-bit dual channel, continuous tracking synchro/
resolver-to-digital converter. It has been designed specifically
for applications where space, weight, and cost are at a premium.
Each 32-lead hybrid device contains two independent Type II servo
loop tracking converters. The ratiometric conversion technique
employed provides excellent noise immunity and tolerance of
long lead lengths.
All components are 100% tested at −55°C, +25°C, and +125°C.
Devices are processed to high reliability screening standards
and receive further levels of testing and screening to ensure
high levels of reliability.
FUNCTIONAL BLOCK DIAGRAM
R
(A)
(A)
HI
REFERENCE
CONDITIONER
R
LO
+V
S
S1 (A)
S2 (A)
HIGH
SPEED
SIN/COS
MULTIPLIER
PHASE-
SENSITIVE
DETECTOR
GND
SYNCHRO/
RESOLVER
CONDITIONER
UP-DOWN
COUNTER
ERROR
AMP
INTEGRATOR
VCO
–V
S
S3 (A)
S4 (A)
BIT
BUILT-IN
TEST
DETECTION
A/B
OE
THREE-
STATE
AD2S44
DB1 (MSB)
TO
OUTPUT
LATCHES
DB14 (LSB)
S1 (B)
S2 (B)
HIGH
SPEED
SIN/COS
MULTIPLIER
SYNCHRO/
RESOLVER
CONDITIONER
PHASE-
SENSITIVE
DETECTOR
UP-DOWN
COUNTER
ERROR
AMP
VCO
INTEGRATOR
S3 (B)
S4 (B)
R
(B)
(B)
HI
REFERENCE
CONDITIONER
R
LO
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1989–2011 Analog Devices, Inc. All rights reserved.