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AD28MSP02KR PDF预览

AD28MSP02KR

更新时间： 2024-02-07 13:47:01
品牌 Logo 应用领域
亚德诺 - ADI 消费电路商用集成电路光电二极管
页数 文件大小 规格书
20页 328K
描述
Voiceband Signal Port

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AD28MSP02KR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOIC-28
针数：28Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.66商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：R-PDSO-G28JESD-609代码：e0
长度：17.9 mm功能数量：1
端子数量：28最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：220
认证状态：Not Qualified座面最大高度：2.65 mm
最大压摆率：40 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mmBase Number Matches：1

AD28MSP02KR 数据手册

 浏览型号AD28MSP02KR的Datasheet PDF文件第1页浏览型号AD28MSP02KR的Datasheet PDF文件第3页浏览型号AD28MSP02KR的Datasheet PDF文件第4页浏览型号AD28MSP02KR的Datasheet PDF文件第5页浏览型号AD28MSP02KR的Datasheet PDF文件第6页浏览型号AD28MSP02KR的Datasheet PDF文件第7页 
AD28msp02  
VFB  
NORM  
VIN  
NORM  
16-BIT SIGMA-DELTA ADC  
SDOFS  
SDO  
NORM  
AUX  
INPUT  
AMP  
ANALOG  
ANTI-ALIASING  
DECIMATION  
FILTER  
DIGITAL  
HIGH-PASS  
FILTER  
1
16  
16  
+20dB  
AMP  
MUX  
SIGMA-DELTA  
MODULATOR  
VFB  
AUX  
AUX  
1.0  
8.0  
kHz  
8.0  
kHz  
VIN  
MHz  
INPUT  
AMP  
DATA/  
CNTRL  
CONTROL  
REGISTER  
SERIAL  
PORT  
VOLTAGE  
REFERENCE  
V
REF  
SCLK  
16-BIT SIGMA-DELTA DAC  
DIGITAL  
ANALOG  
SMOOTHING  
FILTER  
1
ANTI-IMAGING  
16  
16  
16  
DIGITAL  
HIGH-PASS  
FILTER  
VOUT  
P
SIGMA-DELTA  
MODULATOR  
SDI  
INTERPOLATION  
FILTER  
PGA  
VOUT  
N
1.0  
8.0  
8.0  
1.0  
MHz  
MHz  
kHz  
kHz  
OUTPUT  
SDIFS  
CS  
DIFFERENTIAL  
AMP  
Figure 1. AD28msp02 Block Diagram  
The IIR low-pass filter is a 10th-order elliptic filter with a pass-  
band edge at 3.7 kHz and a stopband attenuation of 65 dB at  
4 kHz. This filter has the following specifications:  
The high-pass filter is a 4th-order elliptic filter with a passband  
cutoff at 150 Hz. Stopband attenuation is 25 dB. This filter has  
the following specifications:  
Filter type:  
10th-order low-pass elliptic IIR  
Filter type:  
4th-order high-pass elliptic IIR  
Sample frequency:  
Passband cutoff:*  
Passband ripple:  
Stopband cutoff:  
Stopband ripple:  
40.0 kHz  
3.70 kHz  
±0.2 dB  
4.0 kHz  
Sample frequency: 8.0 kHz  
Passband cutoff:  
Passband ripple:  
Stopband cutoff:  
Stopband ripple:  
150.0 Hz  
±0.2 dB  
100.0 Hz  
–25.00 dB  
–65.00 dB  
*The passband cutoff frequency is defined to be the last point in the passband  
that meets the passband ripple specification.  
(Note that these specifications apply only to this filter, and not to the entire  
ADC. The specifications can be used to perform further analysis of the exact  
characteristics of the filter, for example using a digital filter design software  
package.)  
(Note that these specifications apply only to this filter, and not to the entire  
ADC. The specifications can be used to perform further analysis of the exact  
characteristics of the filter, for example using a digital filter design software  
package.)  
Figure 3 shows the frequency response of the high-pass filter.  
0
Figure 2 shows the frequency response of the IIR low-pass filter.  
0
–20  
–40  
–20  
–40  
–60  
–60  
–80  
–80  
–100  
60  
120  
180  
240  
300  
0
FREQUENCY – Hz  
–100  
2000  
2600  
3200  
3800  
4400  
5000  
Figure 3. High-Pass Filter Frequency Response  
FREQUENCY – Hz  
Passband ripple is ±0.2 dB for the combined effects of the  
ADC’s digital filters (i.e., high-pass filter and IIR low-pass of  
the decimation filter) in the 300 Hz–3400 Hz passband.  
Figure 2. IIR Low-Pass Filter Frequency Response  
High-Pass Filter  
The digital high-pass filter removes frequency components at  
the low end of the spectrum; it attenuates signal energy below  
the passband of the converter. The high-pass filter can be  
bypassed by setting the ADBY bit (Bit 3) of the AD28msp02’s  
control register.  
The output of the ADC is transferred to the AD28msp02’s  
serial port (SPORT) at an 8 kHz rate, for transmission to the  
host DSP processor. Maximum group delay in the ADC will not  
exceed 1 ms in the region from 300 Hz to 3 kHz.  
–2–  
REV. 0  
1234567...20

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