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AD28MSP02KR

更新时间： 2024-01-02 22:16:12

品牌	Logo	应用领域
亚德诺 - ADI		消费电路商用集成电路光电二极管
页数	文件大小	规格书
20页	328K
描述
Voiceband Signal Port

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中文翻译

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技术参数
数据手册

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AD28MSP02KR 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOIC-28
针数：	28	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.66	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	R-PDSO-G28	JESD-609代码：	e0
长度：	17.9 mm	功能数量：	1
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	220
认证状态：	Not Qualified	座面最大高度：	2.65 mm
最大压摆率：	40 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	7.5 mm	Base Number Matches：	1

AD28MSP02KR 数据手册

AD28msp02

Serial Data Output

Each bit of a 16-bit data word is thus clocked into the

AD28msp02 on the falling edge of SCLK (MSB first).

The AD28msp02’s SPORT will begin transmitting data to the

host processor at an 8 kHz rate when the PWDD and PWDA

bits (Bits 4, 5) of the control register are set to 1. In the pro-

gram shown in Figure 6, the instructions

If SDIFS is asserted high again before the end of the present

data word transfer, it is not recognized until the falling edge of

SCLK in the last (LSB) cycle.

AX0 = 0x30; { Write control word to take }

TX0 = AX0; { AD28msp02 out of powerdown }

accomplish this by writing 0x30 to the AD28msp02’s control

trol register write) before the AD28msp02 raises SDOFS and

begins transmitting data; see Figure 11.

(Note: Exact SPORT timing requirements are defined in the

“Specifications” section of this data sheet.)

CONTROL REGISTER

The AD28msp02’s control register configures the device for

various modes of operation including ADC and DAC gain set-

tings, ADC input mux selection, filter bypass, and powerdown.

The AD28msp02’s host processor can read and write to the

control register through the AD28msp02’s serial port (SPORT)

by driving the DATA/CNTRL pin low.

At the 13 MHz MCLK frequency, data is transmitted at an

8 kHz rate with a single 16-bit word transmitted every 125 µs.

While data is being output, the AD28msp02 asserts SDOFS at

an 8 kHz rate. Each 16-bit word transfer begins one serial clock

cycle after SDOFS is asserted.

The control register is cleared (set to 0x0000) when the

AD28msp02 is reset.

Serial Data Input

The host processor must initiate data transfers to the

AD28msp02 by asserting the serial data input frame sync

(SDIFS) high. The 16-bit word transfer begins one serial clock

cycle after SDIFS is asserted. The DATA/CNTRL line must be

driven high when SDIFS is driven high.

Control Register Writes

To write the control register, the host processor must assert

DATA/CNTRL low when it asserts SDIFS. If the MSB of

the bit stream is also low, the SPORT recognizes the incoming

serial data as a new control word and copies it to the

AD28msp02’s control register. The format for the control word

write is shown in Table II; reserved Bits 10-15 must be set to

zero.

The host processor must assert SDIFS shortly after the rising

edge of SCLK and must maintain SDIFS high for one cycle.

Data is then driven from the host processor (to the SDI input)

shortly after the rising edge of the next SCLK and is clocked

into the AD28msp02 on the falling edge of SCLK in that cycle.

Table II. Control Word Write Format

15 14

OG2 OG1

OG0

PWDD PWDA ADBY DABY IMS

IPS

IMS

DABY

ADBY

PWDA

PWDD

Analog input preamplifier select: 1 = insert (+20 dB), 0 = bypass (0 dB)

Analog input multiplexer select: 1 = AUX input, 0 = NORM input

DAC high-pass filter bypass select: 0 = insert, 1 = bypass

ADC high-pass filter bypass select: 0 = insert, 1 = bypass

Powerdown analog: 0 = powerdown, 1 = operating

Powerdown digital: 0 = powerdown, 1 = operating

7–9

10–15

OG2-OG0 Analog output gain setting (for D/A output PGA)

Reserved

Gain

OG2

OG1

OG0

+6 dB

+3 dB

0 dB

–3 dB

–6 dB

–9 dB

–12 dB

–15 dB

Gain settings are accurate within ±0.6 dB.

(Control Register is set to 0x0000 at RESET. Reserved Bits

10–15 must be set to 0 for all Control Register writes.)

–6–

REV. 0

1...3 4 567 8 9...20

中文翻译

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