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AD10465PCB

更新时间： 2024-02-28 23:20:21
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
20页 2425K
描述
Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning

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中文翻译

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AD10465PCB 技术参数

Source Url Status Check Date：2013-05-01 14:56:08.131是否无铅：含铅
是否Rohs认证：不符合生命周期：Active
零件包装代码：QFP包装说明：QFP, LDCC68,1.0SQ
针数：68Reach Compliance Code：not_compliant
ECCN代码：3A991.C.3HTS代码：8542.39.00.01
风险等级：5.64Is Samacsys：N
最大模拟输入电压：2 V最小模拟输入电压：-2 V
转换器类型：ADC, PROPRIETARY METHODJESD-30 代码：S-CQFP-G68
长度：24.13 mm标称负供电电压：-5 V
模拟输入通道数量：3位数：14
功能数量：2端子数量：68
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：2'S COMPLEMENT BINARY输出格式：PARALLEL, WORD
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QFP
封装等效代码：LDCC68,1.0SQ封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：220
电源：3.3,5 V认证状态：Not Qualified
采样速率：65 MHz采样并保持/跟踪并保持：TRACK
座面最大高度：4.45 mm子类别：Analog to Digital Converters
标称供电电压：5 V表面贴装：YES
技术：BIPOLAR温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：24.13 mmBase Number Matches：1

AD10465PCB 数据手册

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AD10465  
VT  
AD10465 on any input by using the other inputs as alternate  
locations for GND or an external resistor. The following chart  
summarizes the impedance options available at each input  
location:  
0.1␮F  
0.1␮F  
ENCODE  
ECL/  
PECL  
AD10465  
ENCODE  
AIN1 = 100 Ω when AIN2 and AIN3 are open.  
AIN1 = 75 Ω when AIN3 is shorted to GND.  
AIN1 = 50 Ω when AIN2 is shorted to GND.  
AIN2 = 200 Ω when AIN3 is open.  
VT  
Figure 7. Differential ECL for Encode  
Jitter Considerations  
AIN2 = 100 Ω when AIN3 is shorted to GND.  
The signal-to-noise ratio (SNR) for an ADC can be predicted.  
When normalized to ADC codes, Equation 1 accurately predicts  
the SNR based on three terms. These are jitter, average DNL  
error, and thermal noise. Each of these terms contributes to the  
noise within the converter.  
AIN2 = 75 Ω when AIN2 to AIN3 has an external resistor of  
300 Ω, with AIN3 shorted to GND.  
AIN2 = 50 Ω when AIN2 to AIN3 has an external resistor of  
100 Ω, with AIN3 shorted to GND.  
AIN3 = 400 Ω.  
AIN3 = 100 Ω when AIN3 has an external resistor of 133 Ω to  
GND.  
1/2  
1+ ε  
+
2N  
AIN3 = 75 Ω when AIN3 has an external resistor of 92 Ω to  
GND.  
2
SNR = −20 × log 2 × π × f  
× t rms  
+
(
)
ANALOG  
J
AIN3 = 50 Ω when AIN3 has an external resistor of 57 Ω to  
(1)  
V  
2  
GND.  
NOISE RMS   
2N  
APPLYING THE AD10465  
Encoding the AD10465  
The AD10465 encode signal must be a high quality, extremely  
low phase noise source, to prevent degradation of performance.  
Maintaining 14-bit accuracy places a premium on encode clock  
phase noise. SNR performance can easily degrade by 3 dB to  
4 dB with 32 MHz input signals when using a high-jitter clock  
source. See Analog Devices’ Application Note AN-501, “Aper-  
ture Uncertainty and ADC System Performance” for complete  
details. For optimum performance, the AD10465 must be clocked  
differentially. The encode signal is usually ac-coupled into the  
ENCODE and ENCODE pins via a transformer or capacitors.  
These pins are biased internally and require no additional bias.  
fANALOG  
tJ RMS  
= analog input frequency.  
= rms jitter of the encode (rms sum of encode  
source and internal encode circuitry).  
ε
= average DNL of the ADC (typically 0.50 LSB).  
= Number of bits in the ADC.  
N
VNOISE RMS = V rms noise referred to the analog input of the  
ADC (typically 5 LSB).  
For a 14-bit analog-to-digital converter like the AD10465, aper-  
ture jitter can greatly affect the SNR performance as the analog  
frequency is increased. The chart below shows a family of curves  
that demonstrates the expected SNR performance of the AD10465  
as jitter increases. The chart is derived from the above equation.  
Shown below is one preferred method for clocking the AD10465.  
The clock source (low jitter) is converted from single-ended to  
differential using an RF transformer. The back-to-back Schottky  
diodes across the transformer secondary limit clock excursions  
into the AD10465 to approximately 0.8 V p-p differential. This  
helps prevent the large voltage swings of the clock from feeding  
through to the other portions of the AD10465, and limits the  
noise presented to the ENCODE inputs. A crystal clock oscillator  
can also be used to drive the RF transformer if an appropriate  
limiting resistor (typically 100 Ω) is placed in the series with  
the primary.  
For a complete discussion of aperture jitter, please consult  
Analog Devices’ Application Note AN-501, “Aperture Uncer-  
tainty and ADC System Performance.”  
71  
A
= 5MHz  
IN  
70  
69  
68  
67  
66  
65  
64  
63  
62  
A
= 10MHz  
IN  
0.1nF  
100⍀ T1-4T  
CLOCK  
SOURCE  
ENCODE  
AD10465  
ENCODE  
HSMS2812  
DIODES  
A
= 20MHz  
= 32MHz  
IN  
Figure 6. Crystal Clock Oscillator, Differential Encode  
A
IN  
61  
60  
0.1  
0.3  
If a low jitter ECL/PECL clock is available, another option is to  
ac-couple a differential ECL/PECL signal to the encode input  
pins as shown below. A device that offers excellent jitter perfor-  
mance is the MC100LVEL16 (or same family) from Motorola.  
0.5  
0.9  
1.3  
1.7  
2.1  
2.5  
2.9  
3.3  
3.7  
0.7  
1.1  
1.5  
1.9  
2.3  
2.7  
3.1  
3.5  
3.9  
RMS CLOCK JITTER – ps  
Figure 8. SNR vs. Jitter  
–10–  
REV. 0  
1...78910111213...20

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