AD10465PCB

更新时间： 2024-02-28 11:24:36

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
20页	2425K
描述
Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning

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技术参数
数据手册

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AD10465PCB 技术参数

Source Url Status Check Date：	2013-05-01 14:56:08.131	是否无铅：	含铅
是否Rohs认证：	不符合	生命周期：	Active
零件包装代码：	QFP	包装说明：	QFP, LDCC68,1.0SQ
针数：	68	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.C.3	HTS代码：	8542.39.00.01
风险等级：	5.64	Is Samacsys：	N
最大模拟输入电压：	2 V	最小模拟输入电压：	-2 V
转换器类型：	ADC, PROPRIETARY METHOD	JESD-30 代码：	S-CQFP-G68
长度：	24.13 mm	标称负供电电压：	-5 V
模拟输入通道数量：	3	位数：	14
功能数量：	2	端子数量：	68
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出位码：	2'S COMPLEMENT BINARY	输出格式：	PARALLEL, WORD
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QFP
封装等效代码：	LDCC68,1.0SQ	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	220
电源：	3.3,5 V	认证状态：	Not Qualified
采样速率：	65 MHz	采样并保持/跟踪并保持：	TRACK
座面最大高度：	4.45 mm	子类别：	Analog to Digital Converters
标称供电电压：	5 V	表面贴装：	YES
技术：	BIPOLAR	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	24.13 mm	Base Number Matches：	1

AD10465PCB 数据手册

AD10465

DEFINITION OF SPECIFICATIONS

Analog Bandwidth

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

Overvoltage Recovery Time

The amount of time required for the converter to recover to

0.02% accuracy after an analog input signal of the specified

percentage of full scale is reduced to midscale.

Power Supply Rejection Ratio

Aperture Delay

The delay between a differential crossing of ENCODE and

ENCODE and the instant at which the analog input is sampled.

The ratio of a change in input offset voltage to a change in power

supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

The ratio of the rms signal amplitude (set at 1 dB below full

scale) to the rms value of the sum of all other spectral compo-

nents, including harmonics but excluding dc. May be reported

in dB (i.e., relative to signal level) or in dBFS (always related

back to converter full scale).

Differential Nonlinearity

The deviation of any code from an ideal 1 LSB step.

Encode Pulsewidth/Duty Cycle

Signal-to-Noise Ratio (without Harmonics)

Pulsewidth high is the minimum amount of time that the

ENCODE pulse should be left in Logic “1” state to achieve

rated performance; pulsewidth low is the minimum time

ENCODE pulse should be left in low state. At a given clock

rate, these specs define an acceptable Encode duty cycle.

The ratio of the rms signal amplitude (set at 1 dB below full

scale) to the rms value of the sum of all other spectral compo-

nents, excluding the first five harmonics and dc. May be reported

in dB (i.e., relative to signal level) or in dBFS (always related

back to converter full scale).

Harmonic Distortion

The ratio of the rms signal amplitude to the rms value of the

worst harmonic component.

Spurious-Free Dynamic Range

The ratio of the rms signal amplitude to the rms value of the

peak spurious spectral component. The peak spurious compo-

nent may or may not be a harmonic.

Integral Nonlinearity

The deviation of the transfer function from a reference line

measured in fractions of 1 LSB using a “best straight line”

determined by a least square curve fit.

Transient Response

The time required for the converter to achieve 0.03% accu-

racy when a one-half full-scale step function is applied to the

analog input.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaranteed limit.

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value of

the worst third order intermodulation product; reported in dBFS.

Maximum Conversion Rate

The encode rate at which parametric testing is performed,

above which converter performance may degrade.

Output Propagation Delay

The delay between a differential crossing of ENCODE and

ENCODE and the time when all output data bits are within

valid logic levels.

t_A

N+3

N+1

N+2

N+4

t_ENC

t_ENCH

N+1

t_ENCL

ENC, ENC

N+2

t_{E, DR}

N+3

N+4

t_OD

N–3

N–2

N–1

D[13:0]

DRY

Figure 1. Timing Diagram

–8–

REV. 0

1...5 6 789 10 11...20

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