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ACS541K

更新时间: 2024-11-11 22:38:59
品牌 Logo 应用领域
英特矽尔 - INTERSIL 驱动器
页数 文件大小 规格书
3页 236K
描述
Radiation Hardened Octal Buffer/ Line Driver Three-State

ACS541K 数据手册

 浏览型号ACS541K的Datasheet PDF文件第2页浏览型号ACS541K的Datasheet PDF文件第3页 
ACS541MS  
Radiation Hardened Octal Buffer/  
Line Driver Three-State  
January 1996  
Features  
Pinouts  
20 LEAD CERAMIC DUAL-IN-LINE  
MIL-STD-1835 DESIGNATOR,  
CDIP2-T20, LEAD FINISH C  
TOP VIEW  
• Devices QML Qualified in Accordance with MIL-PRF-38535  
• Detailed Electrical and Screening Requirements are Contained in  
SMD# 5962-96710 and Intersil’s QM Plan  
• 1.25 Micron Radiation Hardened SOS CMOS  
1
2
3
4
5
6
7
8
9
VCC  
OE2  
OE1  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
20  
19  
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)  
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day  
(Typ)  
18 Y0  
17 Y1  
16 Y2  
15 Y3  
14 Y4  
13 Y5  
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg  
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse  
• Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse  
• Latch-Up Free Under Any Conditions  
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V  
• Input Logic Levels  
12  
Y6  
GND 10  
11 Y7  
- VIL = 30% of VCC Max  
- VIH = 70% of VCC Min  
20 LEAD CERAMIC FLATPACK  
MIL-STD-1835 DESIGNATOR,  
CDFP4-F20, LEAD FINISH C  
TOP VIEW  
• Input Current 1µA at VOL, VOH  
• Fast Propagation Delay . . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ)  
VCC  
OE2  
Y0  
OE1  
A0  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Description  
The Intersil ACS541MS is a Radiation Hardened Octal Buffer/Line  
Driver, with three-state outputs. The output enable pins OE1, OE2 con-  
trol the Three-State outputs. If either enable is high the output will be in a  
high impedance state. For data output both enables must be low.  
A1  
Y1  
A2  
A3  
Y2  
A4  
Y3  
The ACS541MS utilizes advanced CMOS/SOS technology to achieve  
high-speed operation. This device is a member of a radiation hardened,  
high-speed, CMOS/SOS Logic family.  
A5  
Y4  
A6  
Y5  
A7  
Y6  
Y7  
The ACS541MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a  
Ceramic Dual-In-Line package (D suffix).  
GND  
Ordering Information  
PART NUMBER  
5962F9671001VRC  
5962F9671001VXC  
ACS541D/Sample  
ACS541K/Sample  
ACS541HMSR  
TEMPERATURE RANGE  
SCREENING LEVEL  
PACKAGE  
o
o
-55 C to +125 C  
MIL-PRF-38535 Class V  
20 Lead SBDIP  
o
o
-55 C to +125 C  
MIL-PRF-38535 Class V  
20 Lead Ceramic Flatpack  
20 Lead SBDIP  
o
25 C  
Sample  
Sample  
Die  
o
25 C  
20 Lead Ceramic Flatpack  
Die  
o
25 C  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518856  
File Number 4085  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1

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