Datasheet > ACS32201

ACS32201

更新时间： 2022-10-08 16:54:39

品牌	Logo	应用领域
艾迪悌 - IDT		便携式
页数	文件大小	规格书
65页	1267K
描述
PORTABLE CONSUMER DEVICE

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中文翻译

获取价格

数据手册

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ACS32201 数据手册

ACS32201

LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER

3.2. Volume Control

The signal volume can be controlled digitally, across a gain and attenuation range of -95.25dB to 0dB (0.375dB steps).

The level of attenuation is specified by an eight-bit code, ‘DACVOL_x’, where ‘x’ is L, or R. The value “00000000” indi-

cates mute; other values select the number of 0.375dB steps above -95.625dB for the volume level.

The Volume Update bits control the updating of volume control data; when a bit is written as ‘0’, the Left Volume control

associated with that bit is updated whenever the left volume register is written and the Right Volume control is updated

when ever the right volume register is written. When a bit is written as ‘1’, the left volume data is placed into an internal

holding register when the left volume register is written and both the left and right volumes are updated when the right

volume register is written. This enables a simultaneous left and right volume update

Bit

Label

Type

Default

Description

RSVD

Reserved

1 = volume fades between old/new value

0 = volume/mute changes immediately

DACFade

RSVD

5:3

Reserved for future use.

0 = Left DAC volume updated immediately

1 = Left DAC volume held until right DAC volume

R10 (0Ah)

VUCTL

DACVOLU

0 = Left speaker volume updated immediately

1 = Left speaker volume held until right speaker

volume register written.

SPKVOLU

RSVD

Reserved

Table 6. Volume Update Control Register

The output path may be muted automatically when a long string of zero data is received. The length of zeros is pro-

grammable and a detection flag indicates when a stream of zero data has been detected.

Bit

Label

zerodet_flag

RSVD

Type

Default

Description

1 = zero detect length exceeded.

Reserved for future use.

Enable mute if input consecutive zeros exceeds this

length. 0 = 512, 1 = 1k, 2 = 2k, 3 = 4k samples

5:4

zerodetlen

R33 (21h)

Gain Control

(GAINCTL)

RSVD

auto_mute

RSVD

Reserved for future use.

1 = auto mute if detect long string of zeros on input

Reserved for future use.

RSVD

Reserved for future use.

zerodet_flag

1 = zero detect length exceeded.

Table 7. Gain Control Register

IDT CONFIDENTIAL

V0.6 07/11

ACS32201

1...7 8 91011 12 13...65

中文翻译

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与ACS32201相关器件

型号	品牌	获取价格	描述	数据表
ACS32201XNAGYYX	IDT	获取价格	PORTABLE CONSUMER DEVICE
ACS32201XTAGYYX	IDT	获取价格	PORTABLE CONSUMER DEVICE
ACS32D	INTERSIL	获取价格	Radiation Hardened Quad 2-Input OR Gate
ACS32D/SAMPLE-02	RENESAS	获取价格	OR Gate, AC Series, 4-Func, 2-Input, CMOS, CDIP14
ACS32D/SAMPLE-03	RENESAS	获取价格	OR Gate, AC Series, 4-Func, 2-Input, CMOS, CDIP14
ACS32DMSR-03	INTERSIL	获取价格	Radiation Hardened Quad 2-Input OR Gate
ACS32HMSR-03	INTERSIL	获取价格	Radiation Hardened Quad 2-Input OR Gate
ACS32K	INTERSIL	获取价格	Radiation Hardened Quad 2-Input OR Gate
ACS32K/SAMPLE-02	RENESAS	获取价格	AC SERIES, QUAD 2-INPUT OR GATE, CDFP14, CERAMIC, DFP-14
ACS32K/SAMPLE-03	RENESAS	获取价格	OR Gate, AC Series, 4-Func, 2-Input, CMOS, CDFP14

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