ACPL-M21L, ACPL-021L and ACPL-024L
Low Power, 5 MBd Digital CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
ACPL-M21L (single channel SO-5 package), ACPL-021L
(single channel SO-8 package) and ACPL-024L (dual
channel SO-8 package) are optically-coupled logic gates.
The detector IC has CMOS output stage and optical
•ꢀ CMOS output
•ꢀ Wide supply voltage: 2.7 V – 5.5 V
•ꢀ Low power supply current I : 1.1 mA/channel max.
DD
receiver input stage with built-in Schmitt trigger to •ꢀ Low forward current I : 1.6 mA min
F
provide logic-compatible waveforms, eliminating the
need for additional waveshaping.
•ꢀ Speed: 5 MBd typ
•ꢀ Pulse width distortion (PWD): 200 ns max
An internal shield on the ACPL-M21L/021L/024L guar-
•ꢀ Propagation delay skew (tpsk): 220 ns max
antees common mode transient immunity of 25 kV/µs
•ꢀ Propagation delay (tp): 250 ns max
at a common mode voltage of 1000 V. The ACPL-x2xL
optocouplers' series operates from a 2.7 V to 5.5 V
supply with guaranteed AC and DC performance from an
extended temperature range of -40 °C to 105 °C. Glitches
free output upon power-up and power-down of optocou-
pler.
•ꢀ Common mode rejection: 25 kV/μs min at V = 1000 V
CM
•ꢀ Hysteresis: 0.2 mA typ
•ꢀ Temperature range: -40 °C to 105 °C
•ꢀ Safety and regulatory approvals
– UL 1577 recognized – 3750 Vrms for 1 minute for
ACPL-M21L/021L/024L
Functional Diagram
TRUTH TABLE
6
1
– CSA Approval
VDD
VO
Anode
(POSITIVE LOGIC)
– IEC/EN 60747-5-5, Approval for Reinforced Insulation
5
4
LED
ON
VO
HIGH
Applications
3
GND
Cathode
Shield
OFF
LOW
•ꢀ Low isolation of high speed logic systems
•ꢀ Computer peripheral interface
•ꢀ Microprocessor system interface
•ꢀ Ground loop elimination
ACPL-M21L
1
2
3
4
8
7
6
Anode1
VDD
V01
1
8
NC
VDD
VO
2
7
6
Cathode1
Anode
NC
Cathode2
Anode2
V02
3
4
Cathode
NC
•ꢀ Pulse transformer replacement
•ꢀ High speed line receiver
5
5
GND
GND
Shield
Shield
ACPL-021L
ACPL-024L
•ꢀ Power control systems
A 0.1 μF bypass capacitor must be connected between pins Vdd and GND